EP0378427A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
High speed data transfer on a computer system bus
Assignee: International Business Machines Corp
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Filing: 1990-01-11
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Granted: —
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Expires: 2010-01-11
Abstract
Abstract A computer system bus is described which includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both master and slave devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.
Inventors
- 👤 Ravi Kumar Arimilli
- 👤 Sudhir Dhawan
- 👤 George Albert Lerom
- 👤 James Otto Nicholson
- 👤 David William Siegel
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 13:49
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
181 words
A system for transferring data in a computer between a master subsystem (12) and a slave subsystem (14) comprising: a bus (10) coupled to the master subsystem and the slave subsystem for communicating signals therebetween, said bus including means for communicating address, data and control signals, and a clock line in said bus for communicating a normal clock signal under control of the master subsystem, characterised in that said bus includes means for communicating a separate high speed clock signal under control of the master subsystem, and said bus includes means for the slave subsystem to communicate to the master subsystem a transfer mode signal indicative of one or more data transfer capabilities of the slave subsystem, said transfer mode signal comprising a high speed mode signal indicating whether the slave subsystem is capable of transferring data according to said high speed clock signal, wherein the master subsystem, in response to said high speed mode signal, selects whether data is transferred between the master subsystem and the slave subsystem according to said normal clock or according to said high speed clock.
Claim 2
Independent Claim
181 words
A system for transferring data in a computer between a master subsystem (12) and a slave subsystem (14) comprising: a bus (10) coupled to the master subsystem and the slave subsystem for communicating signals therebetween, said bus including means for communicating address, data and control signals, and a clock line in said bus for communicating a normal clock signal under control of the master subsystem, characterised in that said bus includes means for communicating a separate high speed clock signal under control of the master subsystem, and said bus includes means for the slave subsystem to communicate to the master subsystem a transfer mode signal indicative of one or more data transfer capabilities of the slave subsystem, said transfer mode signal comprising a high speed mode signal indicating whether the slave subsystem is capable of transferring data according to said high speed clock signal, wherein the master subsystem, in response to said high speed mode signal, selects whether data is transferred between the master subsystem and the slave subsystem according to said normal clock or according to said high speed clock.
Claim 3
Dependent Claim
69 words
A system as claimed in Claim 1, in which said transfer mode signal includes a transfer speed control signal, said transfer speed control signal being used by the slave subsystem, in the case when the slave subsystem is capable of data transfers according to said high speed clock, to indicate to the master subsystem the maximum rate at which the slave subsystem is capable of making such data transfers.
Claim 4
Independent Claim
71 words
A system as claimed in any preceding claim, in which said transfer mode signal includes a transfer width control signal indicating the maximum data word width which can be transferred by the slave subsystem, and in which the master subsystem, in response to said transfer width control signal, selects a data word width within the capabilities of the slave subsystem for transferring data between the master subsystem and the slave subsystem.
Claim 5
Independent Claim
76 words
A system as claimed in any preceding claim in which said bus includes a ready control line used by the slave subsystem to communicate to the master subsystem, during a data transfer according to said high speed clock signal, whether the slave is ready to complete the transfer of an individual data item, and in which said transfer is not completed by the master until the slave indicates that it is ready to complete said transfer.
Claim 6
Independent Claim
30 words
A system as claimed in any preceding claim, in which the master communicates only one address on the bus during a data transfer according to said high speed clock signal.
Claim 7
Independent Claim
170 words
A device (12) for transferring data on a computer system bus (10), comprising: means for communicating a normal clock signal on a clock line in said bus, means for communicating, on said bus, a high speed clock signal separate from said normal clock signal, means for addressing a second device (14) connected to said bus, means for detecting a transfer mode signal on the bus from said second device, which signal indicates one or more data transfer capabilities of said second device, said transfer mode signal comprising a high speed mode signal indicating whether said second device is capable of transferring data according to said high speed clock signal, means for transferring data to or from said second device according to said normal clock signal, means for transferring data, according to the high speed clock, and means for selecting, in response to said high speed mode signal, whether to transfer data, between said device and said second device, according to the normal clock or according to the high speed clock.
Claim 8
Independent Claim
170 words
A device (12) for transferring data on a computer system bus (10), comprising: means for communicating a normal clock signal on a clock line in said bus, means for communicating, on said bus, a high speed clock signal separate from said normal clock signal, means for addressing a second device (14) connected to said bus, means for detecting a transfer mode signal on the bus from said second device, which signal indicates one or more data transfer capabilities of said second device, said transfer mode signal comprising a high speed mode signal indicating whether said second device is capable of transferring data according to said high speed clock signal, means for transferring data to or from said second device according to said normal clock signal, means for transferring data, according to the high speed clock, and means for selecting, in response to said high speed mode signal, whether to transfer data, between said device and said second device, according to the normal clock or according to the high speed clock.
Claim 9
Independent Claim
128 words
A device (14) for transferring data on a computer system bus (10), comprising: means for detecting a normal clock signal on a clock line in said bus, means for detecting a high speed clock signal, separate from said normal clock signal means for recognising that the device is being addressed on the bus by a second device (12) connected to the bus, means for communicating a transfer mode signal on the bus to said second device, which signal indicates one or more data transfer capabilities of the device, said transfer mode signal comprising a high speed mode signal indicating whether the device is capable of transferring data according to said high speed clock signal, and if so, means for transferring data according to the high speed clock signal.
Claim 10
Independent Claim
128 words
A device (14) for transferring data on a computer system bus (10), comprising: means for detecting a normal clock signal on a clock line in said bus, means for detecting a high speed clock signal, separate from said normal clock signal means for recognising that the device is being addressed on the bus by a second device (12) connected to the bus, means for communicating a transfer mode signal on the bus to said second device, which signal indicates one or more data transfer capabilities of the device, said transfer mode signal comprising a high speed mode signal indicating whether the device is capable of transferring data according to said high speed clock signal, and if so, means for transferring data according to the high speed clock signal.
Claim 11
Independent Claim
136 words
A method for transferring data on a computer system bus (10) between a master subsystem (12) and a slave subsystem (14) said bus including means for communicating a normal clock signal under control of the master subsystem comprising the steps of the master subsystem initiating a data transfer with the slave subsystem, the slave subsystem indicating to the master subsystem, whether the slave can transfer data according to a high speed clock, separate from the normal clock, the master subsystem selecting, in response to said indication, whether to transfer data between the master subsystem and the slave subsystem according to said high speed clock or according to said normal clock, and in the case of a transfer according to said high speed clock, the master subsystem placing such a high speed clock signal on the bus.
Claim 12
Independent Claim
136 words
A method for transferring data on a computer system bus (10) between a master subsystem (12) and a slave subsystem (14) said bus including means for communicating a normal clock signal under control of the master subsystem comprising the steps of the master subsystem initiating a data transfer with the slave subsystem, the slave subsystem indicating to the master subsystem, whether the slave can transfer data according to a high speed clock, separate from the normal clock, the master subsystem selecting, in response to said indication, whether to transfer data between the master subsystem and the slave subsystem according to said high speed clock or according to said normal clock, and in the case of a transfer according to said high speed clock, the master subsystem placing such a high speed clock signal on the bus.
References Cited (Backward Citations)
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