Patent US5337273A successfully refreshed from Google Patents.
US5337273A
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Charge sharing flash clear for memory arrays
Assignee: STMicroelectronics lnc USA
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Filing: 1993-07-30
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Granted: 1994-08-09
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Expires: 2013-07-30
Abstract
Abstract A static random access memory provides interconnection of local wordlines and bit lines to share charge during bulk write operations. Prior to a bulk write cycle, a bit line for each memory cell is driven to a first voltage level. Subsequently, the bit lines and the local wordlines are interconnected for sharing charge between the bit lines and the local wordlines. Next, the bit lines are disconnected from the local wordlines and the bit lines are driven to a second voltage level while the local wordlines are driven to the first voltage level to address the memory cells. Then the bit lines and local wordlines are reconnected to distribute charge from the local wordlines to the bit lines. Lastly, the bit lines are again disconnected from the local wordlines and driven to the first voltage level preparatory to resuming normal operation.
Inventors
- 👤 David C. McClure
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:41
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0891; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C7/18; G11C8/00; G11C8/14; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
129 words
A random access memory, comprising: a plurality of memory cells, arrayed in rows and columns; a wordline for addressing each row of memory cells; a pair of bit lines for transfer of data into and out of each memory cell in a column; a charge distribution line for carrying charge between at least a first bit line from a pair of bit lines and a wordline; a first switch for selectively connecting the charge distribution line to the first bit line; a second switch for selectively connecting the charge distribution line to the wordline; a third switch for selectively connecting the first bit line to a voltage source representing logic one; and a fourth switch for selectively connecting the first bit line to a voltage source representing logic zero.
Claim 2
Dependent Claim
129 words
A random access memory, comprising: a plurality of memory cells, arrayed in rows and columns; a wordline for addressing each row of memory cells; a pair of bit lines for transfer of data into and out of each memory cell in a column; a charge distribution line for carrying charge between at least a first bit line from a pair of bit lines and a wordline; a first switch for selectively connecting the charge distribution line to the first bit line; a second switch for selectively connecting the charge distribution line to the wordline; a third switch for selectively connecting the first bit line to a voltage source representing logic one; and a fourth switch for selectively connecting the first bit line to a voltage source representing logic zero.
Claim 3
Dependent Claim
41 words
A random access memory as set forth in claim 1, and further comprising: a tristateable driver connected to the charge distribution line for controlling voltage on the charge distribution line and for controlling output impedance exhibited to the charge distribution line.
Claim 4
Dependent Claim
32 words
A random access memory as set forth in claim 2, and further comprising: control logic for generating control signals for driving the first, second, third and fourth switches and the tristateable driver.
Claim 5
Dependent Claim
20 words
A random access memory as set forth in claim 3, wherein the first, second, third and fourth switches are transistors.
Claim 6
Dependent Claim
21 words
A random access memory as set forth in claim 4, wherein the random access memory is a static random access memory.
Claim 7
Dependent Claim
43 words
A random access memory as set forth in claim 2, further comprising: a plurality of blocks of memory cells; and a block decoder responsive to a block select signal level comprising a transistor gate connected between the wordline and the charge distribution line.
Claim 8
Dependent Claim
57 words
A random access memory as set forth in claim 6, and further comprising: a main wordline; a main wordline decoder responsive to a select signal for applying a block select level to a wordline; and the main wordline decoder including an inverter connected between a source of a second block select level and the charge distribution line.
Claim 9
Dependent Claim
107 words
In a static random access memory including a plurality of memory cells, each memory cell being addressed along a wordline and accessed after being addressed on a bit line, a method of clearing the memory cells comprising the steps of: during a first period driving a bit line for each memory cell to a first voltage level; during a second period interconnecting the bit lines to wordlines for sharing charge between the bit lines and the wordlines; and during a third period disconnecting the bit lines from the wordlines, driving the bit lines to a second voltage level and driving the wordlines to the first voltage level.
Claim 10
Dependent Claim
107 words
In a static random access memory including a plurality of memory cells, each memory cell being addressed along a wordline and accessed after being addressed on a bit line, a method of clearing the memory cells comprising the steps of: during a first period driving a bit line for each memory cell to a first voltage level; during a second period interconnecting the bit lines to wordlines for sharing charge between the bit lines and the wordlines; and during a third period disconnecting the bit lines from the wordlines, driving the bit lines to a second voltage level and driving the wordlines to the first voltage level.
Claim 11
Dependent Claim
46 words
A method as set forth in claim 8, and further comprising: during a fourth period reconnecting the bit lines and wordlines to distribute charge; and during a fifth period disconnecting the bit lines from the wordlines and driving the bit lines to the first voltage level.
Claim 12
Dependent Claim
34 words
A method as set forth in claim 9, wherein the first voltage level is V cc and corresponds to logic one and the second voltage level is V ss and corresponds to logic zero.
Claim 13
Dependent Claim
39 words
A method as set forth in claim 8, wherein the first period occurs prior to beginning flash clear, the second period corresponds to beginning of flash clear and the third period corresponds to flash clearing of the memory cells.
Claim 14
Dependent Claim
66 words
A method as set forth in claim 9, wherein the first period occurs prior to beginning flash clear, the second period corresponds to beginning of flash clear, the third period corresponds to flash clearing of the memory cells, the fourth period occurs immediately after flash clearing of the memory cells and the fifth period terminates a flash clear cycle and immediately precedes return to normal operation.
Claim 15
Dependent Claim
100 words
A static random access memory comprising: a plurality of memory cells; a plurality of wordlines for addressing the plurality of memory cells; bit lines for transfer of data into and out of the memory cells after being addressed; means for driving a bit line for each memory cell to a first voltage level; means for connecting the bit lines to wordlines for sharing charge between the bit lines and the wordlines; and means for disconnecting the bit lines from the wordlines and for driving the bit lines to a second voltage level and the wordlines to the first voltage level.
Claim 16
Dependent Claim
100 words
A static random access memory comprising: a plurality of memory cells; a plurality of wordlines for addressing the plurality of memory cells; bit lines for transfer of data into and out of the memory cells after being addressed; means for driving a bit line for each memory cell to a first voltage level; means for connecting the bit lines to wordlines for sharing charge between the bit lines and the wordlines; and means for disconnecting the bit lines from the wordlines and for driving the bit lines to a second voltage level and the wordlines to the first voltage level.
Claim 17
Dependent Claim
74 words
A static random access memory as set forth in claim 13, and further comprising: means for reconnecting the bit lines and local wordlines to distribute charge after the bit lines have been driven to the second voltage level and the wordlines have been driven to the first voltage level; and means for disconnecting the bit lines from the wordlines and driving the bit lines to the first voltage level after reconnection has been completed.
Claim 18
Dependent Claim
37 words
A static random access memory as set forth in claim 14, wherein the first voltage level is V cc and corresponds to logic one and the second voltage level is V ss and corresponds to logic zero.
Claim 19
Dependent Claim
28 words
A static random access memory as set forth in claim 15, wherein the means for driving the local wordlines to the first voltage level include a tristateable driver.
Claim 20
Dependent Claim
38 words
A static random access memory as set forth in claim 16, wherein the means for driving the bit lines to a second voltage level include a transistor switch for connecting the bit line to the second voltage level.
Claim 21
Dependent Claim
52 words
A static random access memory as set forth in claim 15, and further comprising transistors connected between the bit lines and voltage sources for providing transistor loads on the bits lines, the transistor loads for the bit lines being used for connecting the wordlines to a proportion of the first voltage level.
Claim 22
Dependent Claim
61 words
A static random access memory as set forth in claim 13, wherein the means for connecting the bit lines to the wordlines for sharing charge between the bit lines and the wordlines include, a charge transmission line; a transmission gate between a bit line and the charge transmission line; and a transmission gate between the charge transmission line and a wordline.
Claim 23
Dependent Claim
33 words
A static random access memory as set forth in claim 19, wherein the means for driving the wordlines to the first voltage level include a tristateable driver connected to the charge transmission line.
Claim 24
Dependent Claim
31 words
A static random access memory as set forth in claim 20, wherein the transmission gate between a bit line and the charge transmission line includes complementary p and n channel transistors.
Claim 25
Dependent Claim
26 words
A static random access memory as set forth in claim 21, wherein the bit line is a complementary bit line from a pair of bit lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |