Patent US5337050A successfully refreshed from Google Patents.
US5337050A
Expired / Lapsed
US
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Serial-to-parallel converter circuit
Assignee: NEC Corp
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Filing: 1993-02-08
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Granted: 1994-08-09
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Expires: 2013-02-08
Abstract
Abstract A serial-to-parallel converter circuit includes a reduced number of gate circuits necessary to configure the circuit. In the converter, each of the register blocks is constituted with an R-S flip-flop circuit including two NAND gates and an NAND gate to select the flip-flop circuit. A decoder selects one of the register blocks according to an accumulation value of serial clocks received by a counter, thereby setting data received via a data input terminal to the selected register block.
Inventors
- 👤 Mitsutoshi Sugawara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 11:35
CPC Classifications
H; H03; H03M; H03M9/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
179 words
A serial-to-parallel converter circuit comprising: a plurality of register blocks, each of the register blocks having a flip-flop circuit developing a function to keep therein data and to output therefrom the data and a gate circuit for receiving as inputs thereto two selection signals for selecting the flip-flop circuit; and an address decoder for receiving as an input thereto address data for selecting, in response to the address data, a predetermined register block from the plurality of register blocks, wherein the flip-flop circuit comprises and R-S flip-flop circuit including a first NAND gate and a second NAND gate, the gate circuit including a third NAND gate connected to a set signal input side of the R-S flip-flop circuit, and wherein the R-S flip-flop circuit is selected depending on set signals inputted to the third NAND gate, wherein the address decoder includes: a counter for receiving as inputs thereto a serial clock and a reset signal, for accumulating the serial clock, and for outputting a result of accumulation of the serial clocks; and a first decoder and a second decoder.
Claim 2
Dependent Claim
179 words
A serial-to-parallel converter circuit comprising: a plurality of register blocks, each of the register blocks having a flip-flop circuit developing a function to keep therein data and to output therefrom the data and a gate circuit for receiving as inputs thereto two selection signals for selecting the flip-flop circuit; and an address decoder for receiving as an input thereto address data for selecting, in response to the address data, a predetermined register block from the plurality of register blocks, wherein the flip-flop circuit comprises and R-S flip-flop circuit including a first NAND gate and a second NAND gate, the gate circuit including a third NAND gate connected to a set signal input side of the R-S flip-flop circuit, and wherein the R-S flip-flop circuit is selected depending on set signals inputted to the third NAND gate, wherein the address decoder includes: a counter for receiving as inputs thereto a serial clock and a reset signal, for accumulating the serial clock, and for outputting a result of accumulation of the serial clocks; and a first decoder and a second decoder.
Claim 3
Dependent Claim
193 words
A serial-to-parallel converter circuit comprising: a plurality of register blocks, each of the register blocks having a flip-flop circuit developing a function to keep therein data and to output therefrom the data and a gate circuit for receiving as inputs thereto two selection signals for selecting the flip-flop circuit; and an address decoder for receiving as an input thereto address data for selecting, in response to the address data, a predetermined register block from the plurality of register blocks, wherein: the flip-flop circuit comprises an R-S flip-flop circuit including a first NAND gate and a second NAND gate; the gate circuit includes an inverter, a third NAND gate and a fourth NAND gate, each of the third and fourth NAND gates being connected on an input side of the R-S flip-flop circuit; and the flip-flop circuit is enabled to be set or reset depending on data inputted to the inverter, wherein the address decoder includes: a counter for receiving as inputs thereto a serial clock and a reset signal, for accumulating the serial clock, and for outputting a result of accumulation of the serial clocks; and a first decoder and a second decoder.
Claim 4
Dependent Claim
193 words
A serial-to-parallel converter circuit comprising: a plurality of register blocks, each of the register blocks having a flip-flop circuit developing a function to keep therein data and to output therefrom the data and a gate circuit for receiving as inputs thereto two selection signals for selecting the flip-flop circuit; and an address decoder for receiving as an input thereto address data for selecting, in response to the address data, a predetermined register block from the plurality of register blocks, wherein: the flip-flop circuit comprises an R-S flip-flop circuit including a first NAND gate and a second NAND gate; the gate circuit includes an inverter, a third NAND gate and a fourth NAND gate, each of the third and fourth NAND gates being connected on an input side of the R-S flip-flop circuit; and the flip-flop circuit is enabled to be set or reset depending on data inputted to the inverter, wherein the address decoder includes: a counter for receiving as inputs thereto a serial clock and a reset signal, for accumulating the serial clock, and for outputting a result of accumulation of the serial clocks; and a first decoder and a second decoder.
Claim 5
Dependent Claim
92 words
A serial-to-parallel converter circuit comprising: a plurality of register blocks, each of the register blocks having a flip-flop circuit developing a function to keep therein data and to output therefrom the data and a gate circuit for receiving as inputs thereto two selection signals for selecting the flip-flop circuit; and an address decoder for receiving as an input thereto address data for selecting, in response to the address data, a predetermined register block from the plurality of register blocks, wherein said plurality of register blocks are coupled together to form a matrix.
Claim 6
Dependent Claim
92 words
A serial-to-parallel converter circuit comprising: a plurality of register blocks, each of the register blocks having a flip-flop circuit developing a function to keep therein data and to output therefrom the data and a gate circuit for receiving as inputs thereto two selection signals for selecting the flip-flop circuit; and an address decoder for receiving as an input thereto address data for selecting, in response to the address data, a predetermined register block from the plurality of register blocks, wherein said plurality of register blocks are coupled together to form a matrix.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |