US5336911A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Seiko Epson Corp
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Filing: 1992-11-12
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Granted: 1994-08-09
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Expires: 2012-11-12
Abstract
Abstract A Bi-MOS semiconductor device of the type having a bipolar device and a plurality of MOS devices formed on a principal surface of a semiconductor aubstrate and a method of producing the same. The device includes a plurality of element isolation regions each thereof being composed of a first semiconductor region formed in the semiconductor substrate and having the same type of conductivity as the semiconductor substrate, and a thick insulation layer formed on the first semiconductor region, and at least one of an emitter electrode and a collector electrode formed in the bipolar device, gate electrodes formed in the MBS devices, a low-resistivity polycrystalline layer formed by a buried contact from one of the MOS devices and a high-resistivity portion formed by a high resistivity polycrystalline silicon layer connected to the low-resistivty polycrystalline silicon layer are formed from a polycrystalline silicon layer formed by the same layer formation.
Inventors
- 👤 Tomoyuki Furuhata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:35
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
311 words
A Bi-MOS type semiconductor device comprising a first bipolar element and at least one of a CMOS element, said CMOS element comprising p- type and n- type MOS transistors, and second bipolar element are provided in one principal surface of a semiconductor substrate having an element isolation region provided in said semiconductor substrate and having a first semiconductor region of a same conductivity type as said semiconductor substrate and a selective insulation layer, wherein: a polycrystalline silicon layer of one conductive type forms at least one of emitter or collector electrodes of at least one of said first and second bipolar elements; a low-resistivity polycrystalline silicon layer forms a gate electrode of said CMOS element; a low-resistivity polycrystalline silicon layer with a buried contact forms an electrode selected from source and drain electrodes of said CMOS element; a metal silicide layer comprised of at least one metal element selected from a group consisting of Ti, W, Mo, Pt and Co is formed on each of diffusion layers forming said source and drain electrodes of said CMOS element and a base region of at least one of said first and second bipolar elements; and a high-resistivity polycrystalline silicon layer forms a high resistive element connected to said low-resistivity polycrystalline silicon layer, said low-resistivity silicon layers being in one layer formation, said element isolation region comprising said first semiconductor region in said semiconductor substrate having the same conductivity type a said semiconductor substrate, an independent second semiconductor region of said same conductivity type contiguous to said first semiconductor region at the bottom thereof and in a semiconductor layer of a conductivity type different from that of said semiconductor substrate, and a selective insulation layer formed on said semiconductor region, and the composition and width of said first semiconductor region, second semiconductor region and selective isolation layer being at least similar with one another.
Claim 2
Dependent Claim
311 words
A Bi-MOS type semiconductor device comprising a first bipolar element and at least one of a CMOS element, said CMOS element comprising p- type and n- type MOS transistors, and second bipolar element are provided in one principal surface of a semiconductor substrate having an element isolation region provided in said semiconductor substrate and having a first semiconductor region of a same conductivity type as said semiconductor substrate and a selective insulation layer, wherein: a polycrystalline silicon layer of one conductive type forms at least one of emitter or collector electrodes of at least one of said first and second bipolar elements; a low-resistivity polycrystalline silicon layer forms a gate electrode of said CMOS element; a low-resistivity polycrystalline silicon layer with a buried contact forms an electrode selected from source and drain electrodes of said CMOS element; a metal silicide layer comprised of at least one metal element selected from a group consisting of Ti, W, Mo, Pt and Co is formed on each of diffusion layers forming said source and drain electrodes of said CMOS element and a base region of at least one of said first and second bipolar elements; and a high-resistivity polycrystalline silicon layer forms a high resistive element connected to said low-resistivity polycrystalline silicon layer, said low-resistivity silicon layers being in one layer formation, said element isolation region comprising said first semiconductor region in said semiconductor substrate having the same conductivity type a said semiconductor substrate, an independent second semiconductor region of said same conductivity type contiguous to said first semiconductor region at the bottom thereof and in a semiconductor layer of a conductivity type different from that of said semiconductor substrate, and a selective insulation layer formed on said semiconductor region, and the composition and width of said first semiconductor region, second semiconductor region and selective isolation layer being at least similar with one another.
Claim 3
Dependent Claim
34 words
A semiconductor device according to claim 1, wherein said emitter electrode is composed of said polycrystalline silicon layer, and said collector electrode is connected to a collector lead-out region that is a metal layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |