Patent US5336904A successfully refreshed from Google Patents.
US5336904A
Expired / Lapsed
US
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Field effect element utilizing resonant-tunneling and a method of manufacturing the same
Assignee: Mitsubishi Electric Corp
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Filing: 1992-04-02
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Granted: 1994-08-09
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Expires: 2012-04-02
Abstract
Abstract A field effect transistor according to the present invention uses a silicon monocrystalline substrate. At least two independent thin amorphous silicon layers are formed in a position for preventing movement of majority carriers in a channel region in the surface of the silicon substrate. Each amorphous silicon layer is between monocrystalline silicon layers. A gate electrode is formed on the surface of the channel region through a gate insulating layer. Thin potential barriers and a potential well are formed in the channel region by at least two amorphous silicon layers. Sharp potential barriers are formed by forming thin amorphous silicon layers, and a field effect transistor utilizing the resonant-tunneling effect with high tunneling efficiency is implemented.
Inventors
- 👤 Shigeru Kusunoki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:25
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/38; H10P14/3802; B; B82; B82Y; B82Y10/00; H10D; H10D30/00; H10D30/60; H10D30/751; H10D64/00; H10D64/01; H10D64/025; H10D64/027; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/2926; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/3466
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
228 words
A field effect transistor, comprising: a substrate having a main surface wherein said main surface of said substrate has a concave part and; a pair of source/drain regions formed on the main surface of said substrate, spaced a predetermined distance apart from each other on either side of the concave part of said substrate; an insulating layer formed on the main surface of said substrate; a gate electrode formed on the surface of said insulating layer; wherein a part of said gate electrode is formed inside said concave part through said insulating layer; a channel region formed in said substrate along a surface of the substrate between said pair of source/drain regions wherein said channel region is formed along a surface of said concave part; and first and second semiconductor layers formed of a material having a bandgap larger than that of silicon in said channel region, spaced a predetermined distance apart from each other and extending to prevent movement of majority carriers moving between said pair of source/drain regions, wherein said substrate includes, at least a first monocrystalline silicon layer and a second monocrystalline silicon layer formed on the surface of said first monocrystalline silicon layer through said first and second semiconductor layers, and wherein said concave part extends through said second monocrystalline silicon layer and through at least a portion of said first monocrystalline silicon layer.
Claim 2
Dependent Claim
228 words
A field effect transistor, comprising: a substrate having a main surface wherein said main surface of said substrate has a concave part and; a pair of source/drain regions formed on the main surface of said substrate, spaced a predetermined distance apart from each other on either side of the concave part of said substrate; an insulating layer formed on the main surface of said substrate; a gate electrode formed on the surface of said insulating layer; wherein a part of said gate electrode is formed inside said concave part through said insulating layer; a channel region formed in said substrate along a surface of the substrate between said pair of source/drain regions wherein said channel region is formed along a surface of said concave part; and first and second semiconductor layers formed of a material having a bandgap larger than that of silicon in said channel region, spaced a predetermined distance apart from each other and extending to prevent movement of majority carriers moving between said pair of source/drain regions, wherein said substrate includes, at least a first monocrystalline silicon layer and a second monocrystalline silicon layer formed on the surface of said first monocrystalline silicon layer through said first and second semiconductor layers, and wherein said concave part extends through said second monocrystalline silicon layer and through at least a portion of said first monocrystalline silicon layer.
Claim 3
Dependent Claim
39 words
The field effect transistor according to claim 1, wherein said first and second semiconductor layers are formed of one material selected from amorphous silicon, gallium phosphide, aluminum phosphide, zinc sulfide, calcium fluoride, silicon oxide, silicon carbide, and cadmium selenide.
Claim 4
Dependent Claim
32 words
The field effect transistor according to claim 1, wherein said first monocrystalline silicon layer and said second monocrystalline silicon layer are formed of silicon substrates having crystal orientations different from each other.
Claim 5
Dependent Claim
204 words
A field effect transistor, comprising: a substrate having a main surface; a pair of source/drain regions formed on the main surface of said substrate, spaced a predetermined distance apart from each other; an insulating layer formed on the main surface of said substrate; a gate electrode formed on the surface of said insulating layer; a channel region formed in said substrate along a surface of the substrate between said pair of source/drain regions; and a quantum well formed from first and second semiconductor layers, said first and second semiconductor layers formed of a material having a bandgap larger than that of silicon in said channel region, spaced a predetermined distance apart from each other and extending to prevent movement of majority carriers moving between said pair of source/drain regions, wherein said substrate includes a first monocrystalline silicon layer and a second monocrystalline silicon layer formed on said first monocrystalline silicon layer through said first and second semiconductor layers, and wherein said second monocrystalline silicon layer, said first semiconductor layer, said first monocrystalline silicon layer, said second semiconductor layer and said second monocrystalline silicon layer are sequentially arranged in said channel region from one of said source/drain regions to the other of said source/drain regions.
Claim 6
Dependent Claim
204 words
A field effect transistor, comprising: a substrate having a main surface; a pair of source/drain regions formed on the main surface of said substrate, spaced a predetermined distance apart from each other; an insulating layer formed on the main surface of said substrate; a gate electrode formed on the surface of said insulating layer; a channel region formed in said substrate along a surface of the substrate between said pair of source/drain regions; and a quantum well formed from first and second semiconductor layers, said first and second semiconductor layers formed of a material having a bandgap larger than that of silicon in said channel region, spaced a predetermined distance apart from each other and extending to prevent movement of majority carriers moving between said pair of source/drain regions, wherein said substrate includes a first monocrystalline silicon layer and a second monocrystalline silicon layer formed on said first monocrystalline silicon layer through said first and second semiconductor layers, and wherein said second monocrystalline silicon layer, said first semiconductor layer, said first monocrystalline silicon layer, said second semiconductor layer and said second monocrystalline silicon layer are sequentially arranged in said channel region from one of said source/drain regions to the other of said source/drain regions.
Claim 7
Dependent Claim
251 words
A field effect transistor, comprising: a substrate having a main surface; a pair of source/drain regions formed on the main surface of said substrate, spaced a predetermined distance apart from each other; an insulating layer formed on the main surface of said substrate; a gate electrode formed on the surface of said insulating layer; a channel region formed in said substrate along a surface of the substrate between said pair of source/drain regions; and a quantum well formed from a semiconductor layer, said semiconductor layer formed of material having a bandgap larger than that of silicon in said channel region, said semiconductor layer having upwardly extending portions spaced a predetermined distance apart from each other and extending to prevent movement of majority carriers moving between said pair of source/drain regions, wherein said substrate includes a first monocrystalline silicon layer formed on a second monocrystalline silicon layer through said semiconductor layer, wherein said second monocrystalline silicon layer, a first upwardly extending portion of said semiconductor layer, said first monocrystalline silicon layer, a second upwardly extending portion of said semiconductor layer and said second monocrystalline silicon layer are sequentially arranged in said channel region from one of said source/drain regions to the other of said source/drain regions, and wherein said second monocrystalline silicon layer includes said pair of source/drain regions and a concave part between said pair of source/drain regions, and wherein said first monocrystalline silicon layer is buried inside said concave part of said first monocrystalline silicon layer through said semiconductor layer.
Claim 8
Dependent Claim
251 words
A field effect transistor, comprising: a substrate having a main surface; a pair of source/drain regions formed on the main surface of said substrate, spaced a predetermined distance apart from each other; an insulating layer formed on the main surface of said substrate; a gate electrode formed on the surface of said insulating layer; a channel region formed in said substrate along a surface of the substrate between said pair of source/drain regions; and a quantum well formed from a semiconductor layer, said semiconductor layer formed of material having a bandgap larger than that of silicon in said channel region, said semiconductor layer having upwardly extending portions spaced a predetermined distance apart from each other and extending to prevent movement of majority carriers moving between said pair of source/drain regions, wherein said substrate includes a first monocrystalline silicon layer formed on a second monocrystalline silicon layer through said semiconductor layer, wherein said second monocrystalline silicon layer, a first upwardly extending portion of said semiconductor layer, said first monocrystalline silicon layer, a second upwardly extending portion of said semiconductor layer and said second monocrystalline silicon layer are sequentially arranged in said channel region from one of said source/drain regions to the other of said source/drain regions, and wherein said second monocrystalline silicon layer includes said pair of source/drain regions and a concave part between said pair of source/drain regions, and wherein said first monocrystalline silicon layer is buried inside said concave part of said first monocrystalline silicon layer through said semiconductor layer.
Claim 9
Dependent Claim
68 words
The field effect transistor according to claim 4, wherein said first monocrystalline silicon layer has a convex part in said channel region, said second monocrystalline silicon layer is formed on both sides of said convex part of said first monocrystalline silicon layer through said first semiconductor layer and second semiconductor layer, and said pair of source/drain regions are formed on the surface of said second monocrystalline silicon layer.
Claim 10
Dependent Claim
39 words
The field effect transistor according to claim 4, wherein said first and second semiconductor layers are formed of one material selected from amorphous silicon, gallium phosphide, aluminum phosphide, zinc sulfide, calcium fluoride, silicon oxide, silicon carbide, and cadmium selenide.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |