Phase lock loops and methods for their operation

Claim 2

A phase lock loop, comprising: a voltage controlled oscillator for generating an output signal having a frequency which is responsive to a control voltage; a phase detector responsive to the output signal and to a reference signal to generate a control signal indicative of a phase difference of the output signal and the reference signal; and a loop filter comprising a charge pump and a filter network, the charge pump being responsive to the control signal and to the control voltage to apply a charge indicative of both the phase difference and the control voltage to the filter network to develop the control voltage.

Claim 3

A phase lock loop as defined in claim 1, wherein the filter network has an admittance which is responsive to the control voltage.

Claim 4

A phase lock loop as defined in claim 2, wherein the charge pump, the loop filter network admittance and the voltage controlled oscillator are responsive to the control voltage such that a given phase difference of the output signal and the reference signal causes a change in the frequency of the output signal which is approximately proportional to the frequency of the output signal.

Claim 5

A phase lock loop as defined in claim 1, wherein the charge pump comprises a bias circuit for applying an initial bias to the filter network to develop an initial control voltage sufficient to start operation of the charge pump.

Claim 6

A phase lock loop as defined in claim 1, wherein the charge pump is responsive to the control signal and to the control voltage to generate current pulses for application to the filter network, the current pulses having a magnitude indicative of the control voltage, and a duration and a direction indicative of the phase difference.

Claim 7

A phase lock loop as defined in claim 5, wherein: the voltage controlled oscillator is responsive to the control voltage such that the output signal frequency has a particular functional dependence on the control voltage; the charge pump is responsive to the control voltage such that the magnitude of the current pulses has a functional dependence on the control voltage which is substantially proportional to the functional dependence of the output signal frequency on the control voltage; and the filter network is responsive to the control voltage such that a resistive admittance of the filter network has a functional dependence on the control voltage which is substantially proportional to the first derivative of the functional dependence of the output signal frequency on the control voltage.

Claim 8

A phase lock loop as defined in claim 6, wherein the filter network is responsive to the control voltage such that a capacitive admittance of the filter network has a functional dependence on the control voltage which is substantially proportional to the product of the reciprocal of the functional dependence of the output signal frequency on the control voltage and the first derivative of the functional dependence of the output signal on the control voltage.

Claim 9

A phase lock loop as defined in claim 5, wherein: the voltage controlled oscillator comprises a plurality of series connected inverters, each inverter supplying a maximum current effectively determined by the control voltage and characteristics of a field effect transistor; the charge pump comprises a switched current source supplying a maximum current effectively determined by the control voltage and characteristics of a field effect transistor; and the filter network comprises a resistive admittance which is responsive to the control voltage and a capacitive admittance.

Claim 10

A phase lock loop as defined in claim 8, wherein each inverter of the voltage controlled oscillator comprises: a first p channel MOSFET having a drain connected to a positive voltage supply, a gate connected to a bias voltage node and a source; a second p channel MOSFET having a drain connected to the source of the first p channel MOSFET, a gate connected to an input terminal of the inverter and a source connected to an output terminal of the inverter; a first n channel MOSFET having a drain connected to the output terminal of the inverter, a gate connected to the input terminal of the inverter and a source; and a second n channel MOSFET having a drain connected to the source of the first n channel MOSFET, a gate connected to a control voltage node and a source connected to ground; and the charge pump comprises: a first p channel MOSFET having a drain connected to the positive voltage supply, a gate connected to the bias voltage node and a source; a second p channel MOSFET having a drain connected to the source of the first p channel MOSFET, a gate coupled to an output terminal of the phase detector and a source connected to the control voltage node; a first n channel MOSFET having a drain connected to the control voltage node, a gate coupled to an output terminal of the phase detector and a source; a second n channel MOSFET having a drain connected to the source of the first n channel MOSFET, a gate connected to the control voltage node and a source connected to ground; and a current mirror for setting the voltage of the bias voltage node.

Claim 11

A phase lock loop as defined in claim 9, wherein the filter network comprises: an n channel MOSFET having a drain, a gate connected to the control voltage node and a source connected to ground; and a capacitor connected between the control voltage node and the drain of the n channel MOSFET.

Claim 12

A phase lock loop as defined in claim 9, wherein the filter network comprises: a p channel MOSFET having a drain connected to the control voltage node, a gate connected to ground and a source; and a capacitor connected between the source of the channel MOSFET and ground.

Claim 13

A phase lock loop as defined in claim 9, wherein the filter network comprises: an n channel MOSFET having a drain connected to the control voltage node, a gate connected to a bias circuit and a source; and a capacitor connected between the source of the n channel MOSFET and ground.

Claim 14

A phase lock loop as defined in claim 12, wherein the bias circuit is operable to bias the gate of the n channel MOSFET at a voltage approximately equal to twice the control voltage plus a threshold shift caused by operation of the source and substrate of the n channel MOSFET at different voltages.

Claim 15

A phase lock loop as defined in claim 1, wherein the loop filter comprises a pair of charge pumps and a filter network, each of the charge pumps being responsive to the control signal and to the control voltage to apply a charge indicative of both the phase difference and the control voltage to the filter network to develop the control voltage.

Claim 16

A phase lock loop as defined in claim 14, wherein: the filter network comprises a resistive admittance and a capacitive admittance; one of the charge pumps applies charge to the resistive admittance to determine a first order response of the phase lock loop; and another of the charge pumps applies charge to the capacitive admittance to determine a second order response of the phase lock loop.

Claim 17

A phase lock loop as defined in claim 15, wherein the filter network further comprises a voltage-to-current converter responsive to a voltage across the capacitive admittance to apply a current to the resistive admittance.

Claim 18

A phase lock loop as defined in claim 16, wherein the voltage-to-current converter has an exponential transconductance characteristic.

Claim 19

A phase lock loop as defined in claim 14, wherein the voltage controlled oscillator comprises d plurality of series connected inverters, each inverter comprising: a first p channel MOSFET having a drain connected to a positive voltage supply, a gate connected to a bias voltage node and a source; a second p channel MOSFET having a drain connected to the source of the first p channel MOSFET, a gate connected to an input terminal of the inverter and a source connected to an output terminal of the inverter; a first n channel MOSFET having a drain connected to the output terminal of the inverter, a gate connected to the input terminal of the inverter and a source; and a second n channel MOSFET having a drain connected to the source of the first n channel MOSFET, a gate connected to a control voltage node and a source connected to ground; each charge pump comprises: a first p channel MOSFET having a drain connected to the positive voltage supply, a gate connected to the bias voltage node and a source; a second p channel MOSFET having a drain connected to the source of the first p channel MOSFET, a gate coupled to an output terminal of the phase detector and a source; a first n channel MOSFET having a drain connected to the source of the second p channel MOSFET, a gate coupled to an output terminal of the phase detector and a source; a second n channel MOSFET having a drain connected to the source of the first n channel MOSFET, a gate connected to the control voltage node and a source connected to ground; and a current mirror for setting the voltage the bias voltage node; a first-of the charge pumps having the source of its second p channel MOSFET connected to the control voltage node, and a second of the charge pumps having the source of its second p channel MOSFET connected to an integrating node, and the filter network comprising: a capacitor connected between the integrating node and ground; an n channel MOSFET connected between the control voltage node and ground; and a voltage-to-current converter connected between the integrating node and the control voltage node.

Claim 20

A phase lock loop as defined in claim 18, wherein the current-to-voltage converter comprises: a plurality of bipolar transistors in a Darlington configuration having a base connected to the integrating node, an emitter connected to ground; and a current mirror connected between a collector of the Darlington configuration and the control voltage node.

Claim 23

A method as defined in claim 20, comprising varying an admittance of the filter network in response to the control voltage.

Claim 24

A method as defined in claim 21, comprising varying the charge applied to the filter network in response to the control voltage such that a given phase difference of the output signal and the reference signal causes a change in the frequency of the output signal which is approximately proportional to the frequency of the output signal.

Claim 25

A method as defined in claim 20, comprising generating current pulses for application to the filter network, the current pulses having a magnitude indicative of the control voltage and a duration and a direction indicative of the phase difference.

Claim 26

A method as defined in claim 23, comprising: generating an output signal having a frequency which is responsive to the control voltage such that the frequency of the output signal has a particular functional dependence on the control voltage; generating current pulses having a magnitude indicative of the control voltage such that the magnitude of the current pulses has a functional dependence on the control voltage which is substantially proportional to the functional dependence of the output signal frequency on the control voltage; and varying a resistive admittance of the filter network in response to the control voltage such that the resistive admittance has a functional dependence on the control voltage which is substantially proportional to the first derivative of the functional dependence of the output signal frequency on the control voltage.

Claim 27

A method as defined in claim 20, comprising applying identical charges indicative of both the phase difference and the control voltage to two distinct nodes of the filter network to develop the control voltage, a response of the filter network to one of the charges determining a first order response of the phase lock loop and a response of the filter network to the other of the charges determining a second order response of the phase lock loop.