Circuit for limiting maximum frequency output of a voltage controlled oscillator

Claim 2

A circuit comprising: a voltage controlled oscillator (VCO), said VCO generating an output signal having an output frequency; a counter having a maximum operating frequency above which said counter no longer accurately performs, said VCO being capable of generating an output signal having an output frequency which exceeds said maximum operating frequency of said counter, said output signal of said VCO being applied to an input of said counter; and means for decreasing said output frequency of said VCO if said frequency exceeds a preset limit, said preset limit being chosen based upon said maximum operating frequency of said counter.

Claim 3

A circuit comprising: a voltage controlled oscillator (VCO), said VCO generating an output signal having an output frequency, wherein said VCO is connected within a phase-locked loop (PLL); a first circuit connected to an output of said VCO and having a maximum operating frequency above which said first circuit no longer accurately performs, said VCO being capable of generating an output signal having an output frequency which exceeds said maximum operating frequency of said first circuit; and means for decreasing said output frequency if said frequency exceeds a preset limit, said preset limit being chosen based upon said maximum operating frequency of said first circuit.

Claim 4

A circuit comprising: a voltage controlled oscillator (VCO), said VCO generating an output signal having an output frequency, wherein said VCO is connected within a phase-locked loop (PLL); a first circuit connected to an output of said VCO and having a maximum operating frequency above which said first circuit no longer accurately performs, said VCO being capable of generating an output signal having an output frequency which exceeds said maximum operating frequency of said first circuit; and means for decreasing said output frequency if said frequency exceeds a preset limit, said preset limit being chosen based upon said maximum operating frequency of said first circuit.

Claim 5

The circuit of claim 2 wherein said means for decreasing said output frequency comprising: a first input terminal connected to receive a first signal corresponding to said frequency of said VCO output signal; a first comparator means for comparing said first signal to a first reference signal and outputting at a first comparator output terminal a decrease frequency signal if said first comparator means detects said frequency of said VCO output signal is greater than a level corresponding to said first reference signal; said decrease frequency signal outputted by said comparator means causing said frequency of said VCO output signal to fall.

Claim 6

The circuit of claim 3 wherein said first comparator output terminal is connected to a voltage generating means for changing a level of a VCO control signal, so that when said decrease frequency signal is generated, said control signal will change to lower said frequency of said VCO output signal.

Claim 7

The circuit of claim 3 wherein said first comparator output terminal is connected to a phase/frequency detector for detecting a difference in phase/frequency between a reference clock signal and a signal corresponding to said frequency of said VCO output signal, said decrease frequency signal causing said phase/frequency detector to output a control signal so as to cause said frequency of said VCO output signal to lower.

Claim 8

The circuit of claim 3 wherein an input terminal of said first comparator means is connected to a control terminal of said VCO.

Claim 9

The circuit of claim 3 wherein, when said first comparator means does not generate said decrease frequency signal, said circuit is transparent to said PLL circuit.

Claim 10

The circuit of claim 3 further comprising a second comparator means for comparing said first signal to a second reference signal and outputting at a second comparator output terminal a second signal indicating that said frequency of said VCO output signal is below a certain frequency, said second signal causing said frequency of said VCO output signal to not be further lowered by an output of said first comparator.

Claim 11

The circuit comprising: a voltage controlled oscillator (VCO), said VCO generating an output signal having an output frequency; means for decreasing said output frequency if said frequency exceeds a preset limit, said preset limit not being based upon a reference clock frequency, wherein said VCO is connected within a phase-locked loop (PLL) and wherein said means for decreasing said output frequency comprises: a first input terminal connected to receive a first signal corresponding to said frequency of said VCO output signal; a first comparator means for comparing said first signal to a first reference signal and outputting at a first comparator output terminal a decrease frequency signal if said first comparator means detects that said frequency of said VCO output signal is greater than a level corresponding to said first reference signal, said decrease frequency signal outputted by said comparator means causing said frequency of said VCO output signal to fall; a second comparator means for comparing said first signal to a second reference signal and outputting at a second comparator output terminal a second signal indicating that said frequency of said VCO output signal is below a certain frequency, said second signal causing said frequency of said VCO output signal to not be further lowered by an output of said first comparator, wherein said decrease frequency signal is applied to a latch to set said latch, and said second signal is applied to said latch to reset said latch, an output of said latch being connected to control said frequency of said VCO output signal in response to a set condition of said latch.

Claim 12

The circuit comprising: a voltage controlled oscillator (VCO), said VCO generating an output signal having an output frequency; means for decreasing said output frequency if said frequency exceeds a preset limit, said preset limit not being based upon a reference clock frequency, wherein said VCO is connected within a phase-locked loop (PLL) and wherein said means for decreasing said output frequency comprises: a first input terminal connected to receive a first signal corresponding to said frequency of said VCO output signal; a first comparator means for comparing said first signal to a first reference signal and outputting at a first comparator output terminal a decrease frequency signal if said first comparator means detects that said frequency of said VCO output signal is greater than a level corresponding to said first reference signal, said decrease frequency signal outputted by said comparator means causing said frequency of said VCO output signal to fall; a second comparator means for comparing said first signal to a second reference signal and outputting at a second comparator output terminal a second signal indicating that said frequency of said VCO output signal is below a certain frequency, said second signal causing said frequency of said VCO output signal to not be further lowered by an output of said first comparator, wherein said decrease frequency signal is applied to a latch to set said latch, and said second signal is applied to said latch to reset said latch, an output of said latch being connected to control said frequency of said VCO output signal in response to a set condition of said latch.

Claim 13

A circuit comprising: a voltage controlled oscillator (VCO), said VCO generating an output signal having an output frequency; means for decreasing said output frequency if said frequency exceeds a preset limit, said preset limit not being based upon a reference clock frequency, wherein said means for decreasing said output frequency comprises: a first input terminal connected to receive a first signal corresponding to said frequency of said VCO output signal; a first comparator means for comparing said first signal to a first reference signal and outputting at a first comparator output terminal a decrease frequency signal if said first comparator means detects that said frequency of said VCO output signal is greater than a level corresponding to said first reference signal, said decrease frequency signal outputted by said first comparator means being applied to a first input terminal of a logic gate means, a second input terminal of said logic gate means being connected to a first output terminal of a phase/frequency detector for detecting a difference in phase/frequency between a reference clock signal and a signal corresponding to said frequency of said VCO output signal, a signal of a first logic level applied to said first or second input terminal of said logic gate means causing said logic gate means to output a signal to lower said VCO output frequency, an output terminal of said logic gate means being connected to an input of a voltage generating means for changing a level of a VCO control signal, so that when said decrease frequency signal is generated by said first comparator means, said VCO control signal will change to lower said frequency of said VCO output signal, wherein, when said first comparator means does not generate said decrease frequency signal, said logic gate means is transparent to an operation of said phase/frequency detector and said VCO.

Claim 14

A circuit comprising: a voltage controlled oscillator (VCO), said VCO generating an output signal having an output frequency; means for decreasing said output frequency if said frequency exceeds a preset limit, said preset limit not being based upon a reference clock frequency, wherein said means for decreasing said output frequency comprises: a first input terminal connected to receive a first signal corresponding to said frequency of said VCO output signal; a first comparator means for comparing said first signal to a first reference signal and outputting at a first comparator output terminal a decrease frequency signal if said first comparator means detects that said frequency of said VCO output signal is greater than a level corresponding to said first reference signal, said decrease frequency signal outputted by said first comparator means being applied to a first input terminal of a logic gate means, a second input terminal of said logic gate means being connected to a first output terminal of a phase/frequency detector for detecting a difference in phase/frequency between a reference clock signal and a signal corresponding to said frequency of said VCO output signal, a signal of a first logic level applied to said first or second input terminal of said logic gate means causing said logic gate means to output a signal to lower said VCO output frequency, an output terminal of said logic gate means being connected to an input of a voltage generating means for changing a level of a VCO control signal, so that when said decrease frequency signal is generated by said first comparator means, said VCO control signal will change to lower said frequency of said VCO output signal, wherein, when said first comparator means does not generate said decrease frequency signal, said logic gate means is transparent to an operation of said phase/frequency detector and said VCO.

Claim 15

The circuit of claim 10, further comprising: a second comparator means for comparing said first signal to a second reference signal and outputting at a second comparator output terminal a second signal indicating that said frequency of said VCO output signal is below a certain frequency, said second signal being connected to said first input terminal of said logic gate means, said second signal causing said logic gate means to generate a signal to cause said frequency of said VCO output signal to not be further lowered.

Claim 16

The circuit of claim 10 wherein said logic gate means comprising: a first logic gate, said first logic gate having a first input terminal connected to said output terminal of said first comparator means, said first logic gate having a second input terminal connected to a first output terminal of said phase/frequency detector, said first logic gate having an output terminal connected to a first input terminal of said voltage generating means, whereby, when said first comparator means generates said decrease frequency signal, said first logic gate also outputs a decrease frequency signal which causes said voltage generating means to decrease said output frequency of said VCO; a second logic gate having a first input terminal connected to said output terminal of said first comparator means, said second logic gate having a second input terminal connected to a second output terminal of said phase/frequency detector, said second logic gate having an output terminal connected to a second input terminal of said voltage generating means, whereby, when said first comparator means generates said decrease frequency signal, said second logic gate blocks any increase frequency signal generated by said phase/frequency detector from being applied to said voltage generating means and allows said voltage generating means to decrease said output frequency of said VCO, wherein, when said first comparator means is not generating a decrease frequency signal, said first logic gate and said second logic gate relay all signals generated by said phase/frequency detector directly to said voltage generating means, causing said output signal of said VCO to be controlled by said phase/frequency detector.

Claim 17

The circuit of claim 2 wherein said first circuit includes a counter.

Claim 18

The circuit of claim 2 wherein said first circuit includes a phase/frequency detector.