Circuit configuration for phase locking

Claim 1

A circuit configuration, comprising a controllable oscillator for issuing an output signal, a loop filter connected to upstream of said controllable oscillator, a controllable charge pump connected to upstream of said loop filter, said charge pump having an output and including two current sources for selectively charging and discharging said loop filter, said current sources being switchable by respective control signals, a phase detector, said phase detector including: a first NAND gate having two inputs and an inverted output, one of said inputs being acted upon by a reference signal and the other of said inputs being acted upon by one of the control signals for said switchable current sources, a second NAND gate having two inputs and an inverted output, one of said inputs being acted upon by the output signal issued by said controllable oscillator and the other of said inputs being acted upon by the other of the control signals for said switchable current sources, first and second flip-flops having setting inputs, outputs and coupled resetting inputs, said setting inputs being connected to a respective one of said inverted outputs of said first and second NAND gates, a third NAND gate having four inputs and an inverted output, said four inputs respectively being connected to said outputs of said flip-flops and said inverted outputs of said first and second NAND gates, said inverted output of said third NAND gate being connected to said coupled resetting inputs of said flip-flops, a fourth NAND gate having inputs and an inverted output, one of said inputs of said fourth NAND gate being acted upon by said inverted output of said third NAND gate, the other of said inputs of said fourth NAND gate respectively being connected to said output of said first flip-flop and said inverted outputs of said first and second NAND gates, one of the control signals for said switchable current sources being present at said inverted output of said fourth NAND gate, and a fifth NAND gate having inputs and an inverted output, said inputs being connected respectively with said output of said second flip-flop and with said inverted outputs of said second and third NAND gates, the other of the control signals for said switchable current sources being present at said inverted output of said fifth NAND gate; and a constant current source connected in parallel with said output of said controllable charge pump.