Phase locked loop with bandwidth ramp

Claim 2

A phase locked loop arranged to receive an input signal having a preamble portion and a data portion, the phase locked loop comprising: A. signal generating means, for providing a response control signal which monotonically decreases in amplitude beginning at a time when the phase locked loop receives the preamble portion and continuing to monotonically decrease during at least a portion of the time that the phase locked loop receives the data portion; and B. loop control means, coupled to the phase locked loop and the signal generating means, for adjusting the response time of the phase locked loop in accordance with the amplitude of the response control signal.

Claim 3

Apparatus as in claim 1 wherein the loop control means additionally comprises: a loop filter, coupled to receive the response control signal, and responsive to the response control signal such that the bandwidth of the loop filter decreases in accordance with the monotonic amplitude change in the response control signal.

Claim 4

Apparatus as in claim 1 where the loop means additionally comprises: gain control means, coupled to receive the response control signal, for adjusting the gain of the phase locked loop such that the gain decreases in accordance with the monotonic amplitude change in the response control signal.

Claim 5

For use with a disk drive, a phase locked loop, arranged to receive a digital input signal from the disk drive, the input signal having a preamble portion and a data portion, for providing a digital clock signal which is phase locked to the preamble portion, the phase locked loop comprising: A. a voltage-controlled oscillator (VCO) having a voltage input control and an output signal; B. a phase detector, coupled to receive a reference signal and the VCO output signal, and providing pulsed lead and lag output signals; C. a capacitor; D. a charge pump, coupled to receive the lead and lag signals, for incrementally discharging the capacitor when a pulse is received from the lead signal, indicating that the reference signal is leading the VCO output signal, and for incrementally charging the capacitor when a pulse is received on the lag signal, indicating that the reference signal is lagging the VCO output signal, the charge pump also having an increment control input which controls the magnitude of the incremental charge or incremental discharge; and E. means for adjusting the increment control input of the charge pump so that it monotonically decreases from an initial relatively high value at a first time when the phase locked loop begins to receive the preamble portion, to a later relatively lower value at a second time when the phase locked loop stops receiving the preamble portion, the time difference between the first and second times at least as long as a loop time constant equal to the reciprocal of a natural frequency of the phase locked loop.

Claim 6

For use with a disk drive, a phase locked loop, arranged to receive a digital input signal from the disk drive, the input signal having a preamble portion and a data portion, for providing a digital clock signal which is phase locked to the preamble portion, the phase locked loop comprising: A. a voltage-controlled oscillator (VCO) having a voltage input control and an output signal; B. a phase detector, coupled to receive a reference signal and the VCO output signal, and providing pulsed lead and lag output signals; C. a capacitor; D. a charge pump, coupled to receive the lead and lag signals, for incrementally discharging the capacitor when a pulse is received from the lead signal, indicating that the reference signal is leading the VCO output signal, and for incrementally charging the capacitor when a pulse is received on the lag signal, indicating that the reference signal is lagging the VCO output signal, the charge pump also having an increment control input which controls the magnitude of the incremental charge or incremental discharge; and E. means for adjusting the increment control input of the charge pump so that it monotonically decreases from an initial relatively high value at a first time when the phase locked loop begins to receive the preamble portion, to a later relatively lower value at a second time when the phase locked loop stops receiving the preamble portion, the time difference between the first and second times at least as long as a loop time constant equal to the reciprocal of a natural frequency of the phase locked loop.

Claim 7

A phase locked loop arranged to receive a digital input signal from a disk drive, the input signal having a preamble portion and a data portion, the phase locked loop providing a digital clock signal which is phase locked to the preamble portion, the phase locked loop comprising: A. signal generating means, for providing a response control signal which exponentially decreases in amplitude beginning at a time when the phase locked loop receives the preamble portion and continuing to exponentially decrease during at least a portion of the time that the phase locked loop receives the data portion; and B. loop control means, coupled to the phase locked loop and to the signal generating means, for adjusting the response time of the phase locked loop in accordance with the amplitude of the response control signal.

Claim 8

A phase locked loop arranged to receive a digital input signal from a disk drive, the input signal having a preamble portion and a data portion, the phase locked loop providing a digital clock signal which is phase locked to the preamble portion, the phase locked loop comprising: A. signal generating means, for providing a response control signal which exponentially decreases in amplitude beginning at a time when the phase locked loop receives the preamble portion and continuing to exponentially decrease during at least a portion of the time that the phase locked loop receives the data portion; and B. loop control means, coupled to the phase locked loop and to the signal generating means, for adjusting the response time of the phase locked loop in accordance with the amplitude of the response control signal.

Claim 9

Apparatus as in claim 5 wherein the phase lock loop additionally comprises: i. a voltage-controlled oscillator (VCO) having a voltage input control and an output signal; ii. a phase detector, coupled to receive a reference signal and the VCO output signal, and providing pulsed lead and lag output signals; and iii. a capacitor, and wherein the loop control means additionally comprises: iv. a charge pump, coupled to receive the lead and lag signals, and the response control signal, for incrementally discharging the capacitor when a pulse is received from the lead signal, indicating that the reference signal is leading the VCO output signal, and for incrementally charging the capacitor when a pulse is received on the lag signal, indicating that the reference signal is lagging the VCO output signal, the charge pump also having an increment control input which receives the response control signal to control the magnitude of the incremental charge or incremental discharge.