Bipolar bandwidth switch for use in a phase-locked loop

Claim 2

A circuit for controlling impedance between first and second switched terminals, including: first supply terminal means for receiving a first supply potential; second supply terminal means for receiving a second supply potential; first switched terminal means; second switched terminal means; differential means having a first control terminal coupled to the first switched terminal means and a second control terminal coupled to the second switched terminal means for controlling first and second currents as a function of a difference between potentials applied to the first and second switched terminal means; first current mirror means coupled between the differential means and the second switched terminal means for controlling current flow between the first supply terminal means and the second switched terminal means as a function of the first current; second current mirror means coupled between the differential means and the second switched terminal means for controlling current flow between the second switched terminal means and the second supply terminal means as a function of the second current; and control means for controlling current flow through the differential means, wherein the second switched terminal means is driven to a low impedance state with respect to the first switched terminal means when the control means causes current flow through the differential means, and the second switched terminal means is driven to a high impedance state with respect to the first switched terminal means when the control means prevents current flow through the differential means.

Claim 3

The circuit of claim 1 wherein the differential means includes: a first transistor, for controlling the first current, having first and second terminals coupled between the first and second supply terminal means, and the first control terminal coupled to the first switched terminal means; and a second transistor, for controlling the second current, having first and second terminals coupled between the first and second supply terminal means, and the second control terminal coupled to the second switched terminal means.

Claim 4

The circuit of claim 2 wherein the first and second transistors have their second terminals interconnected.

Claim 5

The circuit of claim 2 wherein the first and second transistors comprise bipolar transistors.

Claim 6

The circuit of claim 3 wherein the first and second transistors of the differential means includes NPN bipolar transistors.

Claim 7

The circuit of claim 1 wherein the first current mirror means includes: a first transistor, through which the first current flows, having first and second terminals coupled between the first supply terminal means and the differential means, and a control terminal; and a second transistor having first and second terminals coupled between the first supply terminal means and the second switched terminal means, and a control terminal coupled to the control terminal of the first transistor.

Claim 8

The circuit of claim 6 wherein the first and second transistors of the first current mirror means comprise bipolar transistors.

Claim 9

The circuit of claim 7 wherein the first and second transistors of the first current mirror means comprise PNP bipolar transistors.

Claim 10

The circuit of claim 1 wherein the second current mirror means comprises: a first transistor, through which the second current flows, havin first and second terminals coupled between the first supply terminal means and the differential means and a control terminal coupled to the first terminal; a second transistor having a first terminal, a second terminal coupled to the first supply terminal means, and a control terminal coupled to the control terminal of the first transistor; a third transistor having a first terminal connected to the first terminal of the second transistor, a second terminal coupled to the second supply terminal means, and a control terminal coupled to the first terminal; and a fourth transistor having first and second terminals coupled between the second switched terminal means and the second supply terminal means, and a control terminal coupled to the control terminal of the third transistor.

Claim 11

The circuit of claim 9 wherein the first, second, third and fourth transistors of the second current means comprise bipolar transistors.

Claim 12

The circuit of claim 10 wherein the first and second transistors of the second current mirror means comprise PNP bipolar transistors, and the third and fourth transistors comprise NPN bipolar transistors.

Claim 13

The circuit of claim 1 wherein the control means includes: input terminal means for receiving digital control signals; current source means coupled between the differential means and the second supply terminal means for controlling flow of the first and second current through the differential means; and switching means coupled between the input terminal means and the current source means for controlling the current source means, the switching means switching the current source means ON and causing the circuit to be driven to its low impedance state when a first digital signal is received at the input terminal means, and switching the current source means OFF and causing the circuit to be driven to its high impedance state when a second digital signal is received at the input terminal means.

Claim 14

The circuit of claim 12 wherein the switching means includes: second differential means having third and fourth control terminals coupled to the input terminal means for controlling third and fourth currents; third current mirror means coupled between the differential means and the current source means for controlling the current source means as a function of the third current; and fourth current mirror means coupled between the differential means and the current source means for controlling the current source means as a function of the fourth current.

Claim 15

The circuit of claim 13 wherein the second differential means of the switching means includes: a first transistor, for controlling the third current, having first and second terminals coupled between the first and second supply terminal means, and the third control terminal coupled to the input terminal means; and a second transistor, for controlling the fourth current, having first and second terminals coupled between teh first and second supply terminal means, and the fourth control terminal coupled to the input terminal means.

Claim 16

The circuit of claim 14 wherein the first and second transistors of the second differential means have their second terminals interconnected.

Claim 17

The circuit of claim 14 wherein the first and second transistors of the second differential means comprise bipolar transistors.

Claim 18

The circuit of claim 13 wherein the third current mirror means of the switching means includes: a first transistor, through which the third current flows, having first and second terminals coupled between the first supply terminal means and the differential means, and a control terminal coupled to the first terminal; a second transistor having first and second terminals coupled between the first and second supply terminal means, and a control terminal coupled to the control terminal of the first transistor; and a third transistor having first and second terminals coupled between the current source means and the second supply terminal means, and a control terminal coupled to the first terminal of the second transistor.

Claim 19

The circuit of claim 17 wherein the first, second and third transistors of the third current mirror means comprise bipolar transistors.

Claim 20

The circuit of claim 13 wherein the fourth current mirror means of the switching means includes: a first transistor, through which the fourth current flows, having first and second terminals coupled between the first supply terminal means and the second differential means, and a control terminal coupled to the first terminal; a second transistor having a first terminal, a second terminal coupled to the first supply terminal means, and a control terminal coupled to the control terminal of the first transistor; and a third transistor having a first terminal coupled to the first terminal of the second transistor, a second terminal coupled to the second supply terminal means, and a control terminal coupled to the first terminal and to the current source means.

Claim 21

The circuit of claim 19 wherein the first, second and third transistors of the fourth current mirror means comprise bipolar transistors.

Claim 22

A phase-locked loop, including: phase comparator means for comparing phases of input and output signals and for providing a phase difference signal as a function thereof; oscillator means responsive to the phase comparator means for providing an output signal as a function of the phase difference signal; a bandwidth filter network formed by a plurality of circuit elements; and bandwidth switch means responsive to digital control signals for selectively coupling elements of the bandwidth filter network between the phase comparator means and the oscillator means to control loop bandwidth, including: first supply terminal means for receiving a first supply potential; second supply terminal means for receiving a second supply potential; first switched terminal means coupled to the bandwidth filter network; second switched terminal means coupled to the bandwidth filter network; differential means having a first control terminal coupled to the first switched terminal means and a second control terminal coupled to the second switched terminal means, for controlling first and second currents as a function of a difference between potentials applied to the first and second switched terminal means; first current mirror means coupled between the differential means and the second switched terminal means for controlling current flow between the first supply terminal means and the second switched terminal means as a function of the first current; second current mirror means coupled between the differential means and the second switched terminal means for controlling current flow between the second switched terminal means and the second supply terminal means as a function of a second current; and control means responsive to the digital control signals for controlling current flow through the differential means, wherein the second switched terminal means is driven to a low impedence state with respect to the first switched terminal means thereby causing the loop to have a first bandwidth when the control means receives a first control signal and causes current flow through the differential means, and the second switched terminal means is driven to a high impedence state with respect to the first switched terminal means thereby causing the loop to have a second bandwidth when the control means receives a second control signal and prevents current flow through the differential means.

Claim 23

A phase-locked loop, including: phase comparator means for comparing phases of input and output signals and for providing a phase difference signal as a function thereof; oscillator means responsive to the phase comparator means for providing an output signal as a function of the phase difference signal; a bandwidth filter network formed by a plurality of circuit elements; and bandwidth switch means responsive to digital control signals for selectively coupling elements of the bandwidth filter network between the phase comparator means and the oscillator means to control loop bandwidth, including: first supply terminal means for receiving a first supply potential; second supply terminal means for receiving a second supply potential; first switched terminal means coupled to the bandwidth filter network; second switched terminal means coupled to the bandwidth filter network; differential means having a first control terminal coupled to the first switched terminal means and a second control terminal coupled to the second switched terminal means, for controlling first and second currents as a function of a difference between potentials applied to the first and second switched terminal means; first current mirror means coupled between the differential means and the second switched terminal means for controlling current flow between the first supply terminal means and the second switched terminal means as a function of the first current; second current mirror means coupled between the differential means and the second switched terminal means for controlling current flow between the second switched terminal means and the second supply terminal means as a function of a second current; and control means responsive to the digital control signals for controlling current flow through the differential means, wherein the second switched terminal means is driven to a low impedence state with respect to the first switched terminal means thereby causing the loop to have a first bandwidth when the control means receives a first control signal and causes current flow through the differential means, and the second switched terminal means is driven to a high impedence state with respect to the first switched terminal means thereby causing the loop to have a second bandwidth when the control means receives a second control signal and prevents current flow through the differential means.

Claim 24

The phase-locked loop of claim 21 wherein the phase comparator means, oscillator means, and bandwidth switch means are fabricated on an integrated circuit.

Claim 25

The phase-locked loop of claim 22 wherein the phase comparator means, oscillator means, and bandwidth switch means are fabricated on the integrated circuit using a bipolar technology.

Claim 26

The phase-lock loop of claim 21 wherein the control means includes: input terminal means for receiving the digital control signals; current source means coupled between the differential means and the second supply terminal means for controlling flow of the first and second currents through the differential means; and switching means coupled between the input terminal means and the current source means for controlling the current source means, the switching means switching the current source means ON and causing the bandwidth switch means to be driven to its low impedence state when the first digital signal is received at the input terminal means, and switching the current source means OFF and causing the bandwidth switch means to be driven to its high impedence state when the second digital signal is received at the input terminal means.