Patent US5333276A successfully refreshed from Google Patents.
US5333276A
Expired / Lapsed
US
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Method and apparatus for priority selection of commands
Assignee: Intel Corp
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Filing: 1991-12-27
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Granted: 1994-07-26
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Expires: 2011-12-27
Abstract
Abstract A method and apparatus for minimizing processor idle time resulting from the transfer of data between the processor and a resource. An intelligent First In First Out (FIFO) queuing scheme provides a basis for the transfer of data between a host bus and a system bus or between a bus and a resource. The FIFO posts write requests and provides an acknowledgement back to an originating resource on the host bus that the write request has been received. This acknowledgement enables the processor to continue processing. The FIFO further provides for detection of conditions where posted information may be processed out of First In First Out order and conditions where FIFO registers may be read from or data fields overwritten. This capability additionally minimizes idle time by reducing the number of posted items that need to be written to a resource during a read cycle to that resource.
Inventors
- 👤 Edward Solari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:27
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
97 words
A method of controlling access to a resource in a computer system, comprising the steps of: receiving a write command followed by a first command, wherein said write command and said first command are directed to said resource; storing a priority information corresponding to said commands in a memory means; determining whether said first command is a priority command based on said priority information; and dispatching said first command before dispatching said write command to said resource if said first command is a priority command, such that said resource receives said first command before said write command.
Claim 2
Independent Claim
97 words
A method of controlling access to a resource in a computer system, comprising the steps of: receiving a write command followed by a first command, wherein said write command and said first command are directed to said resource; storing a priority information corresponding to said commands in a memory means; determining whether said first command is a priority command based on said priority information; and dispatching said first command before dispatching said write command to said resource if said first command is a priority command, such that said resource receives said first command before said write command.
Claim 3
Dependent Claim
21 words
The method of claim 1 wherein said step of receiving receives said write command and said first command from a processor.
Claim 4
Dependent Claim
30 words
The method of claim 2, wherein said first command is a read command comprising a first address in said resource, said read command specifying a read operation in said resource.
Claim 5
Dependent Claim
70 words
The method of claim 3 wherein said read operation comprises the steps of: determining a third write command in said buffer means wherein said address of said third write command is equal to said first address; retrieving said data element corresponding to said third write command from said buffer means; and sending said data element corresponding to said third write command to said processor in response to said read command.
Claim 6
Dependent Claim
26 words
The method of claim 1, wherein said first command is a second write command comprising a second data element and a second address in said resource.
Claim 7
Dependent Claim
31 words
The method of claim 5 further comprising the step of sending an acknowledgement signal corresponding to said second write command to said processor after said step of dispatching said first command.
Claim 8
Dependent Claim
31 words
The method of claim 6 further comprising the step of storing said second write command in a buffer means if said first command is determined not to be a priority command.
Claim 9
Dependent Claim
44 words
The method of claim 7 further comprising the steps of: determining whether a system bus coupled to said buffer means and said resource is idle; and dispatching said second write command to said resource over said system bus if said system bus is idle.
Claim 10
Independent Claim
112 words
A method of accessing a resource in a computer system, said resource including at least one addressable memory location, said method comprising the steps of: receiving a first write command followed by a second write command, each of said write commands comprising a data element and an address in said resource; storing said first write command in a buffer means; determining whether said address of said first write command is equal to said address of said second write command; and overwriting said first write command in said buffer means with said second write command if said address of said first write command is equal to said address of said second write command.
Claim 11
Independent Claim
112 words
A method of accessing a resource in a computer system, said resource including at least one addressable memory location, said method comprising the steps of: receiving a first write command followed by a second write command, each of said write commands comprising a data element and an address in said resource; storing said first write command in a buffer means; determining whether said address of said first write command is equal to said address of said second write command; and overwriting said first write command in said buffer means with said second write command if said address of said first write command is equal to said address of said second write command.
Claim 12
Dependent Claim
38 words
The method of claim 9 further comprising the step of storing said second write command in said buffer means if said address of said first write command is not equal to said address of said second write command.
Claim 13
Dependent Claim
40 words
The method of claim 10 further comprising the steps of: determining whether a system bus coupled to said buffer means and said resource is idle; and transferring said second write command to said resource if said system bus is idle.
Claim 14
Dependent Claim
21 words
The method of claim 11 wherein said step of receiving receives said write command and said first command from a processor.
Claim 15
Dependent Claim
24 words
The method of claim 12 further comprising the step of sending a first acknowledgment signal corresponding to said first write command to said processor.
Claim 16
Dependent Claim
24 words
The method of claim 13 further comprising the step of sending a second acknowledgment signal corresponding to said second write command to said processor.
Claim 17
Dependent Claim
176 words
A circuit for controlling access to a resource in a computer system, comprising: input flow control means for receiving a write command followed by a first command, wherein said write command and said first command are directed to said resource, said input flow control means transferring said write command over a first bus and said first command over a second bus; first buffer means for receiving said write command over said first bus, said first buffer means storing said write command; second buffer means for receiving said first command over said second bus, said second buffer means storing said first command; and output flow control means for controlling dispatch of said write command in said first buffer means to said resource, said output flow control means controlling dispatch of said first command in said second buffer means to said resource, said output flow control means causing said first command to be dispatched prior to causing said write command to be dispatched to said resource such that said resource receives said first command before said write command.
Claim 18
Dependent Claim
176 words
A circuit for controlling access to a resource in a computer system, comprising: input flow control means for receiving a write command followed by a first command, wherein said write command and said first command are directed to said resource, said input flow control means transferring said write command over a first bus and said first command over a second bus; first buffer means for receiving said write command over said first bus, said first buffer means storing said write command; second buffer means for receiving said first command over said second bus, said second buffer means storing said first command; and output flow control means for controlling dispatch of said write command in said first buffer means to said resource, said output flow control means controlling dispatch of said first command in said second buffer means to said resource, said output flow control means causing said first command to be dispatched prior to causing said write command to be dispatched to said resource such that said resource receives said first command before said write command.
Claim 19
Dependent Claim
38 words
The circuit of claim 15 further comprising a processor for sending said write command and said first command over a host bus, said input flow control means receiving said first command and said command over said host bus.
Claim 20
Dependent Claim
33 words
The circuit of claim 15 further comprising a memory means for storing a priority information corresponding to said write commands, said input flow control means retrieving said priority information from said memory means.
Claim 21
Dependent Claim
33 words
The circuit of claim 17 wherein said input flow control means determines that said first command is a priority command based on said priority information prior to dispatching to said second buffer means.
Claim 22
Dependent Claim
30 words
The circuit of claim 18, wherein said first command is a read command comprising a first address in said resource from which a first data element is to be read.
Claim 23
Dependent Claim
36 words
The circuit of claim 18, wherein said first command is a second write command comprising a second data element and a second address in said resource into which said second data element is to be written.
Claim 24
Dependent Claim
30 words
The circuit of claim 20 wherein said input flow control means sends an acknowledgment signal corresponding to said second write command to said processor after receiving said second write command.
Claim 25
Dependent Claim
43 words
The circuit of claim 18 wherein said input flow control means receives a third write command, determines that said third write command is not a priority command based on said priority information and stores said third write command in said first buffer means.
Claim 26
Dependent Claim
25 words
The circuit of claim 22 wherein said output flow control means dispatches said third write command to said resource when said system bus is idle.
Claim 27
Dependent Claim
115 words
A circuit for processing a plurality of write commands to a resource in a computer system, said resource including at least one addressable memory location, each of said write commands comprising a data element and an address in said resource, said circuit comprising: input flow control means for receiving said write commands including a first write command followed by a second write command; and storing means for storing said first write command in a buffer means under control of said input flow control means, said storing means overwriting said first write command with said second write command if said address of said first write command is equal to said address of said second write command.
Claim 28
Dependent Claim
115 words
A circuit for processing a plurality of write commands to a resource in a computer system, said resource including at least one addressable memory location, each of said write commands comprising a data element and an address in said resource, said circuit comprising: input flow control means for receiving said write commands including a first write command followed by a second write command; and storing means for storing said first write command in a buffer means under control of said input flow control means, said storing means overwriting said first write command with said second write command if said address of said first write command is equal to said address of said second write command.
Claim 29
Dependent Claim
44 words
The circuit of claim 24 further comprising a processor, said processor sending said first write command and said second write command over a host bus, said input flow control means receiving said first write command and said second write command over said host bus.
Claim 30
Dependent Claim
24 words
The circuit of claim 25 wherein said input flow control means sends an acknowledgment signal corresponding to said second write command to said processor.
Claim 31
Dependent Claim
58 words
The circuit of claim 24 wherein said input flow control means receives a third write command, said input flow control means causing said third write command to be stored in a second entry in said buffer means on determining that the address of said third write command is not equal to said address of said first write command.
Claim 32
Dependent Claim
24 words
The circuit of claim 27 wherein said input flow control means sends an acknowledgment signal corresponding to said third write command to said processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-25 | 1998-01-24 | 1998-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-25 | 2002-01-24 | 2002-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-25 | 2006-01-24 | 2006-07-26 | $7700.00 | Window Closed / Lapsed |