US5179679A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus and method for permitting reading of data from an external memory when data is stored in a write buffer in the event of a cache read miss
Assignee: Individual
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Filing: 1991-07-26
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Granted: 1993-01-12
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Expires: 2011-07-26
Abstract
Abstract A microprocessor is described which includes on a single substrate a central processing unit (CPU), write buffer and cache memory. The write buffer includes storage in each of its sections for a bit which indicates a hit/miss condition for the write cycle data stored in that section of the write buffer. If all these bits indicate that the new data in the write buffer has also been written into the cache memory, then read cycles are permitted before the data in the write buffer is written to external memory.
Inventors
- 👤 Kenneth D. Shoemaker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 06:23
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G06F12/0897
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
174 words
A microprocessor comprising: a central processing unit (CPU); a cache memory coupled to said CPU; a write buffer for providing buffering of write cycle data which is to be transferred over an external bus from said CPU to an external memory during a write cycle; comparator means coupled to said CPU for determining if addresses associated with said write cycle data match any addresses associated with data stored in said cache memory; storage means for storing bits of information representative of said determination made by said comparator means, said storage means being coupled to said comparator means; and logic means coupled to receive said bits from said storage means for enabling said microprocessor to read data from said external memory when said data is not located in said cache memory and said bits are in a predetermined state that indicates whether each of the addresses associated with said write cycle data matches an address associated with data stored in said cache memory, said microprocessor being disabled from reading data from said external memory otherwise.
Claim 2
Dependent Claim
174 words
A microprocessor comprising: a central processing unit (CPU); a cache memory coupled to said CPU; a write buffer for providing buffering of write cycle data which is to be transferred over an external bus from said CPU to an external memory during a write cycle; comparator means coupled to said CPU for determining if addresses associated with said write cycle data match any addresses associated with data stored in said cache memory; storage means for storing bits of information representative of said determination made by said comparator means, said storage means being coupled to said comparator means; and logic means coupled to receive said bits from said storage means for enabling said microprocessor to read data from said external memory when said data is not located in said cache memory and said bits are in a predetermined state that indicates whether each of the addresses associated with said write cycle data matches an address associated with data stored in said cache memory, said microprocessor being disabled from reading data from said external memory otherwise.
Claim 3
Dependent Claim
17 words
The microprocessor defined by claim 1 wherein said storage means comprises a part of said write buffer.
Claim 4
Dependent Claim
27 words
The microprocessor defined by claim 1 including additional means coupled to said storage means for changing the state of said bits upon occurrence of a predetermined condition.
Claim 5
Dependent Claim
23 words
The microprocessor defined by claim 3 wherein said predetermined condition comprises the writing of data into said cache memory from said external memory.
Claim 6
Dependent Claim
19 words
The microprocessor defined by claim 3 wherein said predetermined condition comprises the remapping of data in said cache memory.
Claim 7
Dependent Claim
30 words
The microprocessor defined by claim 1 wherein signals are coupled to said logic means from said write buffer to indicate whether said write buffer is storing said write cycle data.
Claim 8
Dependent Claim
37 words
The microprocessor defined by claim 1 wherein said write buffer comprises a first-in-first-out (FIFO) register having a plurality of sections, each section storing write cycle data and including a bit location for storing one of said bits.
Claim 9
Dependent Claim
149 words
A microprocessor including: a cache memory; a write buffer for temporarily storing data to be written into an external memory, said write buffer having a plurality of sections for storing data and addresses; a bit location associated with each of said sections of said write buffer for storing a bit representative of a hit/miss condition, said hit/miss condition indicating whether an address stored in said write buffer corresponds to an address stored in said cache memory; and logic means coupled to said bit locations for permitting said microprocessor to read a data item from said external memory when said data item is not located in said cache memory and said bits are in a predetermined state that indicates whether each of the addresses stored in said write buffer matches an address stored in said cache memory, said microprocessor not being permitted to read data from said external memory otherwise.
Claim 10
Dependent Claim
149 words
A microprocessor including: a cache memory; a write buffer for temporarily storing data to be written into an external memory, said write buffer having a plurality of sections for storing data and addresses; a bit location associated with each of said sections of said write buffer for storing a bit representative of a hit/miss condition, said hit/miss condition indicating whether an address stored in said write buffer corresponds to an address stored in said cache memory; and logic means coupled to said bit locations for permitting said microprocessor to read a data item from said external memory when said data item is not located in said cache memory and said bits are in a predetermined state that indicates whether each of the addresses stored in said write buffer matches an address stored in said cache memory, said microprocessor not being permitted to read data from said external memory otherwise.
Claim 11
Dependent Claim
35 words
The microprocessor defined by claim 8 including masking means for masking said bits in said logic means, said masking being determined by the presence or absence of data in said section of said write buffer.
Claim 12
Independent Claim
119 words
A method of operating a microprocessor coupled to a external memory, said microprocessor having a write buffer and a cache memory, said method comprising the steps of: storing in said write buffer write cycle data to be written into said external memory; determining by said microprocessor whether address correspondence exists for said write cycle data and data stored in said cache memory; storing by said microprocessor for said write cycle data information representing said hit or miss; and permitting said microprocessor to read data from said external memory in the event of a cache read miss while write cycle data is present in said write buffer; otherwise, said microprocessor not being permitted to read data from said external memory.
Claim 13
Independent Claim
119 words
A method of operating a microprocessor coupled to a external memory, said microprocessor having a write buffer and a cache memory, said method comprising the steps of: storing in said write buffer write cycle data to be written into said external memory; determining by said microprocessor whether address correspondence exists for said write cycle data and data stored in said cache memory; storing by said microprocessor for said write cycle data information representing said hit or miss; and permitting said microprocessor to read data from said external memory in the event of a cache read miss while write cycle data is present in said write buffer; otherwise, said microprocessor not being permitted to read data from said external memory.
Claim 14
Dependent Claim
142 words
A computer system comprising; a central processing unit (CPU); a cache memory coupled to said CPU; an external memory coupled to said CPU; a storage means for temporarily storing a plurality of data items to be written into said external memory, said storage means being coupled to receive said data items from said CPU, said storage means including a bit means for indicating whether each of said data items is present in said cache memory; and logic means coupled to said storage means and said CPU for permitting said CPU to read an additional data item from said external memory when said additional data item is not located in said cache memory and said bit means indicates that said plurality of data items are present in said cache memory, said CPU not being permitted to read data from said external memory otherwise.
Claim 15
Dependent Claim
142 words
A computer system comprising; a central processing unit (CPU); a cache memory coupled to said CPU; an external memory coupled to said CPU; a storage means for temporarily storing a plurality of data items to be written into said external memory, said storage means being coupled to receive said data items from said CPU, said storage means including a bit means for indicating whether each of said data items is present in said cache memory; and logic means coupled to said storage means and said CPU for permitting said CPU to read an additional data item from said external memory when said additional data item is not located in said cache memory and said bit means indicates that said plurality of data items are present in said cache memory, said CPU not being permitted to read data from said external memory otherwise.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-01-12 | 1996-07-13 | 1997-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-01-12 | 2000-07-13 | 2001-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-01-12 | 2004-07-13 | 2005-01-12 | $7700.00 | Window Closed / Lapsed |