Patent US5331226A successfully refreshed from Google Patents.
US5331226A
Expired / Lapsed
US
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Logic cell for field programmable gate array having optional input inverters
Assignee: Xilinx Inc
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Filing: 1992-07-23
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Granted: 1994-07-19
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Expires: 2012-07-23
Abstract
Abstract According to the present invention, logic cells in a logic device include optional inverters on each input to the cell. This selective inversion allows the designer to use inverters without consuming resources available for other functions, and eliminates the need for output inverters. Since any number of inputs to the cell can be inverted, the cell can decode any address equally fast, and a designer can therefore rely on the time required to decode an address regardless the ratio and arrangement of 0's and 1's (inversions and noninversions) in the address. Also a signal which fans out from an output port and is inverted at some destinations and not others is handled easily with the present invention, because providing inverters on all inputs allows full flexibility.
Inventors
- 👤 F. Erich Goetting
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:09
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736; H03K19/20; H03K19/21; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
108 words
A field programmable logic device comprising: a plurality of logic cells each having a plurality of input leads; a plurality of interconnect lines; for at least one of said input leads an optional inverter having: an optional inverter input terminal which can be connected to at least one of said interconnect lines by a corresponding at least one antifuse, an optional inverter output terminal which connects to at least one of said input leads, and means to provide on said optional inverter output terminal a selected one of a signal on said optional inverter input terminal and the complement of said signal on said optional inverter input terminal.
Claim 2
Dependent Claim
108 words
A field programmable logic device comprising: a plurality of logic cells each having a plurality of input leads; a plurality of interconnect lines; for at least one of said input leads an optional inverter having: an optional inverter input terminal which can be connected to at least one of said interconnect lines by a corresponding at least one antifuse, an optional inverter output terminal which connects to at least one of said input leads, and means to provide on said optional inverter output terminal a selected one of a signal on said optional inverter input terminal and the complement of said signal on said optional inverter input terminal.
Claim 3
Dependent Claim
56 words
A field programmable logic device as in claim 1 in which said optional inverter comprises: an inverter having an inverter input terminal connected to said optional inverter input terminal and having an inverter output terminal; means for selectively connecting one of said inverter output terminal and said inverter input terminal to said optional inverter output terminal.
Claim 4
Dependent Claim
94 words
A field programmable logic device as in claim 2 in which said means for selectively connecting comprises: a first pass transistor connected between said inverter input terminal and said optional inverter output terminal; a second pass transistor connected between said inverter output terminal and said optional inverter output terminal; and a memory cell having true and complement outputs, one of said true and complement outputs connected to the control terminal of said first pass transistor, and the other of said true and complement outputs connected to the control terminal of said second pass transistor.
Claim 5
Dependent Claim
20 words
A field programmable logic device as in claim 3 in which said memory cell is part of a shift register.
Claim 6
Dependent Claim
25 words
A field programmable logic device as in claim 4 in which said shift register includes memory cells for controlling other parts of said logic cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-18 | 1998-01-17 | 1998-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-18 | 2002-01-17 | 2002-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-18 | 2006-01-17 | 2006-07-19 | $7700.00 | Window Closed / Lapsed |