Multi-bit sigma-delta analog-to-digital converter with reduced sensitivity to DAC nonlinearities

Claim 2

A multi-bit sigma-delta analog-to-digital converter with improved performance comprising: a sigma-delta modulator including a quantizer and a digital-to-analog converter, for receiving an analog input signal and for providing a digitized signal having a plurality of bits ordered from a most significant bit, to a second most significant bit, to at least one lower-order bit including a least significant bit, said digital-to-analog converter receiving a plurality of feedback bits including said most significant bit and one of said at least one lower-order bit and providing a feedback signal of the sigma-delta modulator in response thereto; a prefilter coupled to said sigma-delta modulator, for receiving said plurality of bits of said digitized signal except for said plurality of feedback bits, and performing a predetermined transfer function thereon to provide a pre-filtered signal; a summing device coupled to said quantizer and to said prefilter, having a positive input terminal for receiving said digitized signal, a negative input terminal for receiving said pre-filtered signal, and an output; and a decimation filter coupled to said summing device, having an input coupled to said output of said second summing device, and an output for providing a digital output of the analog-to-digital converter.

Claim 3

The analog-to-digital converter of claim 1 wherein said sigma-delta modulator is characterized as being a first-order sigma-delta modulator.

Claim 4

The analog-to-digital converter of claim 1 wherein said sigma-delta modulator is characterized as being a second-order sigma-delta modulator.

Claim 5

The analog-to-digital converter of claim 1 wherein said predetermined transfer function of said prefilter provides an overall transfer function of said analog-to-digital converter substantially identical to transfer function of a corresponding analog-to-digital converter which provides all of said plurality of bits to said digital-to-analog converter.

Claim 6

The analog-to-digital converter of claim 1 wherein an order of said decimation filter exceeds an order of said sigma-delta modulator by one.

Claim 7

The analog-to-digital converter of claim 1 wherein said second bit is said least significant bit.

Claim 8

A multi-bit sigma-delta analog-to-digital converter with improved performance comprising: a first summing device having a positive input terminal for receiving an analog input signal, a negative input for receiving a feedback signal, and an output for providing an error signal; a filter having an input for receiving said output of said first summing device, and an output for providing a filtered signal; a quantizer coupled to said filter, having an input for receiving said filtered signal, and an output providing a digitized signal having a plurality of bits ordered from a most significant bit, to a second most significant bit, to at least one lower-order bit including a least significant bit; a digital-to-analog converter coupled to said quantizer, having inputs for receiving respective ones of a plurality of feedback bits of said digitized signal including said most significant bit and one of said at least one lower-order bit, and an output for providing said feedback signal; a prefilter coupled to said quantizer, for receiving said plurality of bits of said digitized signal except for said plurality of feedback bits, and performing a predetermined transfer function thereon to provide a pre-filtered signal; a second summing device coupled to said quantizer and to said prefilter, having a positive input terminal for receiving said digitized signal, a negative input terminal for receiving said pre-filtered signal, and an output; and a decimation filter coupled to said second summing device, having an input coupled to said output of said second summing device, and an output for providing a digital output of the analog-to-digital converter.

Claim 9

A multi-bit sigma-delta analog-to-digital converter with improved performance comprising: a first summing device having a positive input terminal for receiving an analog input signal, a negative input for receiving a feedback signal, and an output for providing an error signal; a filter having an input for receiving said output of said first summing device, and an output for providing a filtered signal; a quantizer coupled to said filter, having an input for receiving said filtered signal, and an output providing a digitized signal having a plurality of bits ordered from a most significant bit, to a second most significant bit, to at least one lower-order bit including a least significant bit; a digital-to-analog converter coupled to said quantizer, having inputs for receiving respective ones of a plurality of feedback bits of said digitized signal including said most significant bit and one of said at least one lower-order bit, and an output for providing said feedback signal; a prefilter coupled to said quantizer, for receiving said plurality of bits of said digitized signal except for said plurality of feedback bits, and performing a predetermined transfer function thereon to provide a pre-filtered signal; a second summing device coupled to said quantizer and to said prefilter, having a positive input terminal for receiving said digitized signal, a negative input terminal for receiving said pre-filtered signal, and an output; and a decimation filter coupled to said second summing device, having an input coupled to said output of said second summing device, and an output for providing a digital output of the analog-to-digital converter.

Claim 10

The analog-to-digital converter of claim 7 wherein said second bit is said least significant bit.

Claim 11

A multi-bit sigma-delta analog-to-digital converter with improved performance comprising: a first summing device having a positive input terminal for receiving an analog input signal, a negative input for receiving a feedback signal, and an output for providing a first error signal; a first filter having an input for receiving said output of said first summing device, and an output for providing a first filtered signal; a second summing device having a positive input terminal for receiving said first filtered signal, a negative input for receiving said feedback signal, and an output for providing a second error signal; a second filter having an input for receiving said output of said second summing device, and an output for providing a second filtered signal; a quantizer coupled to said second filter, having an input for receiving said second filtered signal, and an output providing a digitized signal having a plurality of bits ordered from a most significant bit, to a second most significant bit, to at least one lower-order bit including a least significant bit; a digital-to-analog converter coupled to said quantizer, having inputs for receiving respective ones of a plurality of feedback bits of said digitized signal including said most significant bit and one of said at least one lower-order bit, and an output for providing said feedback signal; a prefilter coupled to said quantizer, for receiving said plurality of bits of said digitized signal except for said plurality of feedback bits, and performing a predetermined transfer function thereon to provide a pre-filtered signal; a third summing device coupled to said quantizer and to said prefilter, having a positive input terminal for receiving said digitized signal, a negative input terminal for receiving said pre-filtered signal, and an output; and a decimation filter coupled to said third summing device, having an input for coupled to said output of said third summing device, and an output for providing a digital output of the analog-to-digital converter.

Claim 12

A multi-bit sigma-delta analog-to-digital converter with improved performance comprising: a first summing device having a positive input terminal for receiving an analog input signal, a negative input for receiving a feedback signal, and an output for providing a first error signal; a first filter having an input for receiving said output of said first summing device, and an output for providing a first filtered signal; a second summing device having a positive input terminal for receiving said first filtered signal, a negative input for receiving said feedback signal, and an output for providing a second error signal; a second filter having an input for receiving said output of said second summing device, and an output for providing a second filtered signal; a quantizer coupled to said second filter, having an input for receiving said second filtered signal, and an output providing a digitized signal having a plurality of bits ordered from a most significant bit, to a second most significant bit, to at least one lower-order bit including a least significant bit; a digital-to-analog converter coupled to said quantizer, having inputs for receiving respective ones of a plurality of feedback bits of said digitized signal including said most significant bit and one of said at least one lower-order bit, and an output for providing said feedback signal; a prefilter coupled to said quantizer, for receiving said plurality of bits of said digitized signal except for said plurality of feedback bits, and performing a predetermined transfer function thereon to provide a pre-filtered signal; a third summing device coupled to said quantizer and to said prefilter, having a positive input terminal for receiving said digitized signal, a negative input terminal for receiving said pre-filtered signal, and an output; and a decimation filter coupled to said third summing device, having an input for coupled to said output of said third summing device, and an output for providing a digital output of the analog-to-digital converter.

Claim 13

The analog-to-digital converter of claim 9 wherein said second bit is said least significant bit.

Claim 14

A multi-bit sigma-delta analog-to-digital converter with improved performance comprising: means for subtracting a feedback signal from an analog input signal to provide an error signal; means for filtering said error signal to provide a filtered signal; means for quantizing said filtered signal into a first digitized signal having a plurality of bits ordered from a most significant bit, to a second most significant bit, to at least one lower-order bit including a least significant bit; means for converting a plurality of feedback bits of said first digitized signal including said most significant bit and one of said at least one lower-order bit into said feedback signal; means coupled to said quantizer, for filtering said plurality of bits of said digitized signal except for said plurality of feedback bits to provide a pre-filtered signal; means for subtracting said pre-filtered signal from said first digitized signal to provide a second digitized signal; and means for resampling said second digitized signal to provide a digital output of the analog-to-digital converter.

Claim 15

A multi-bit sigma-delta analog-to-digital converter with improved performance comprising: means for subtracting a feedback signal from an analog input signal to provide an error signal; means for filtering said error signal to provide a filtered signal; means for quantizing said filtered signal into a first digitized signal having a plurality of bits ordered from a most significant bit, to a second most significant bit, to at least one lower-order bit including a least significant bit; means for converting a plurality of feedback bits of said first digitized signal including said most significant bit and one of said at least one lower-order bit into said feedback signal; means coupled to said quantizer, for filtering said plurality of bits of said digitized signal except for said plurality of feedback bits to provide a pre-filtered signal; means for subtracting said pre-filtered signal from said first digitized signal to provide a second digitized signal; and means for resampling said second digitized signal to provide a digital output of the analog-to-digital converter.

Claim 16

The analog-to-digital converter of claim 11 wherein said converting means comprises a digital-to-analog converter.