US5326712A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing a thin film transistor
Assignee: Samsung Display Co Ltd
•
Filing: 1992-12-03
•
Granted: 1994-07-05
•
Expires: 2012-12-03
Abstract
Abstract A method for manufacturing a semiconductor device which utilizes anodic oxidation. A first semiconductor layer of a first conductive type is formed on an insulating substrate, a highly doped second semiconductor layer of the first conductive type is formed on the first semiconductor layer, and then an anti-oxidizing pattern is formed on the second semiconductor layer to expose a predetermined portion of the second semiconductor layer. After forming the anti-oxidizing pattern, anodic oxidation is performed to oxidize the exposed portion of the second semiconductor layer. Instead of employing a conventional plasma etching process for removing the portion of the ohmic contact layer which is not in contact with the source and drain electrodes, the portion of the ohmic contact layer to be removed is subjected to anodic oxidation, to thereby form an anodic oxidation layer, thus facilitating removal of the unnecessary portions of the ohmic contact layer without the use of a plasma etching step. Accordingly, the problems resulting from the use of a plasma etching process can be avoided, so that a TFT having a high reliability can be obtained.
Inventors
- 👤 Byung-seong Bae
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 23:39
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/60; H10D30/67; H10D30/674; H10D30/6755; H10D30/0321; H10D30/6704; H10D30/6713; H10D30/6741; H10D30/6743; H10D30/6745; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6314; H10P14/6324; H10P14/69; H10P14/692; H10P14/6938; H10P14/6939; H10P14/69391; H10P14/69393; H10P32/00; H10P32/30; H10P32/302; H10P76/00; H10P76/20; H10P76/204; H10P76/2041; Y; Y10; Y10S; Y10S148/00; Y10S148/117; Y10S148/15
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
168 words
A method for manufacturing a TFT comprising the steps of: forming a gate electrode on a glass substrate; forming a gate insulating layer to cover said gate electrode; sequentially forming a first material layer for forming a semiconductor layer on said gate insulating layer and a second material layer which is highly doped with an impurity; forming an anti-oxidizing pattern on said second material layer to expose a portion of said second material layer on said gate electrode; performing anodic oxidation after forming said anti-oxidizing pattern to oxidize said exposed portion of said second material layer, thereby obtaining an anodic oxidation layer; removing said anti-oxidizing pattern; forming a mask pattern to cover said anodic oxidation layer formed on said gate electrode and simultaneously patterning said first and second material layers by employing said mask pattern; and forming symmetrical source and drain electrodes, which center on said anodic oxidation layer formed on said gate electrode, to cover said patterned first and second material layers after removing said mask pattern.
Claim 2
Independent Claim
168 words
A method for manufacturing a TFT comprising the steps of: forming a gate electrode on a glass substrate; forming a gate insulating layer to cover said gate electrode; sequentially forming a first material layer for forming a semiconductor layer on said gate insulating layer and a second material layer which is highly doped with an impurity; forming an anti-oxidizing pattern on said second material layer to expose a portion of said second material layer on said gate electrode; performing anodic oxidation after forming said anti-oxidizing pattern to oxidize said exposed portion of said second material layer, thereby obtaining an anodic oxidation layer; removing said anti-oxidizing pattern; forming a mask pattern to cover said anodic oxidation layer formed on said gate electrode and simultaneously patterning said first and second material layers by employing said mask pattern; and forming symmetrical source and drain electrodes, which center on said anodic oxidation layer formed on said gate electrode, to cover said patterned first and second material layers after removing said mask pattern.
Claim 3
Dependent Claim
32 words
A method for manufacturing a TFT as claimed in claim 1, wherein said first material layer is made of a material selected from a group consisting of hydrogenized amorphous silicon and polysilicon.
Claim 4
Dependent Claim
26 words
A manufacturing method for a TFT as claimed in claim 1, wherein said source and drain electrodes are comprised of a metal capable of anodic oxidation.
Claim 5
Dependent Claim
34 words
A method for manufacturing a TFT as claimed in claim 3, wherein said metal capable of anodic oxidation is a metal selected from a group consisting of Al, Ta, Ti, Mo, W and Nb.
Claim 6
Independent Claim
172 words
A method for manufacturing a thin film transistor, comprising the steps of: forming a gate electrode on a substrate; forming an insulating layer on said gate electrode and adjacent surface portions of said substrate; forming a semiconductor layer on said insulating layer; forming an ohmic contact semiconductor layer on said semiconductor layer; forming an anti-oxidizing layer on said ohmic contact semiconductor layer; patterning said anti-oxidizing layer to expose a portion of said ohmic contact semiconductor layer located above said gate electrode; anodic oxidizing said exposed portion of said ohmic contact semiconductor layer, to thereby form an anodic oxidation layer; removing said patterned anti-oxidizing layer; patterning said semiconductor layer and said ohmic contact semiconductor layer to form a patterned structure having an upper surface and sidewalls, and including said anodic oxidation layer; forming a conductive layer on said upper surface and sidewalls of said patterned structure and adjacent surface portions of said insulating layer; and, patterning said conductive layer to form source and drain electrodes on opposite sides of said anodic oxidation layer.
Claim 7
Independent Claim
172 words
A method for manufacturing a thin film transistor, comprising the steps of: forming a gate electrode on a substrate; forming an insulating layer on said gate electrode and adjacent surface portions of said substrate; forming a semiconductor layer on said insulating layer; forming an ohmic contact semiconductor layer on said semiconductor layer; forming an anti-oxidizing layer on said ohmic contact semiconductor layer; patterning said anti-oxidizing layer to expose a portion of said ohmic contact semiconductor layer located above said gate electrode; anodic oxidizing said exposed portion of said ohmic contact semiconductor layer, to thereby form an anodic oxidation layer; removing said patterned anti-oxidizing layer; patterning said semiconductor layer and said ohmic contact semiconductor layer to form a patterned structure having an upper surface and sidewalls, and including said anodic oxidation layer; forming a conductive layer on said upper surface and sidewalls of said patterned structure and adjacent surface portions of said insulating layer; and, patterning said conductive layer to form source and drain electrodes on opposite sides of said anodic oxidation layer.
Claim 8
Dependent Claim
28 words
The method as set forth in claim 5, wherein said semiconductor layer is made of a material selected from a group consisting of hydrogenized amorphous silicon and polysilicon.
Claim 9
Dependent Claim
21 words
The method as set forth in claim 6, wherein said ohmic contact semiconductor layer is made of a doped semiconductor material.
Claim 10
Dependent Claim
25 words
The method as set forth in claim 5, wherein said source and drain electrodes are positioned symmetrically on opposite sides of said anodic oxidation layer.
References Cited (Backward Citations)
JPS587874A
Cited
JPS58127345A
Cited
JPS5914673A
Cited
US4624737A
Cited
US5084399A
Cited
US4885258A
Cited
JPS6449272A
Cited
US5053354A
Cited
US5010027A
Cited
US5075237A
Cited
US5202274A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-04 | 1998-01-03 | 1998-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-04 | 2002-01-03 | 2002-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-04 | 2006-01-03 | 2006-07-05 | $7700.00 | Window Closed / Lapsed |