US5325508A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Processor that performs memory access in parallel with cache access
Assignee: Dell USA LP
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Filing: 1993-05-07
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Granted: 1994-06-28
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Expires: 2013-05-07
Abstract
Abstract A computer system includes an accessible memory controller, an accessible cache controller, and circuitry for accessing the accessible memory controller and the accessible cache controller simultaneously. Certain preferred embodiments of the present invention also include a deassertable miss line, that is, a line which when deasserted indicates that the data was found in the cache and that the memory access should be cancelled.
Inventors
- 👤 Terry J. Parks
- 👤 Keith D. Matteson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:19
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0877; G06F12/0884
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
235 words
A computer system having a central processing unit (CPU) for processing data a main memory electrically connected to the CPU for storing the data and for providing the data to the CPU upon request, and a cache memory electrically connected to the CPU for storing the data and for providing the data to the CPU upon request; said system comprising: means, electrically connected to said CPU and to said cache memory, for allowing said CPU to access data which is stored in said cache memory; means, electrically connected to said CPU and to said main memory, for allowing said CPU to access data which is stored in said main memory concurrently and in parallel with said cache memory means allowing said CPU to access data which is stored in said cache memory; and means, electrically connected to said cache memory means and to said main memory means for determining whether data requested by said CPU is stored in said cache memory, and if said requested data is stored in said cache memory, disabling said main memory means accessing said requested data which is stored in main memory; wherein said main memory means continue to access said requested data from said main memory if said requested data is not stored in said cache memory; and wherein no delay in accessing said main memory is created by said concurrent and parallel access by said cache memory means.
Claim 2
Dependent Claim
235 words
A computer system having a central processing unit (CPU) for processing data a main memory electrically connected to the CPU for storing the data and for providing the data to the CPU upon request, and a cache memory electrically connected to the CPU for storing the data and for providing the data to the CPU upon request; said system comprising: means, electrically connected to said CPU and to said cache memory, for allowing said CPU to access data which is stored in said cache memory; means, electrically connected to said CPU and to said main memory, for allowing said CPU to access data which is stored in said main memory concurrently and in parallel with said cache memory means allowing said CPU to access data which is stored in said cache memory; and means, electrically connected to said cache memory means and to said main memory means for determining whether data requested by said CPU is stored in said cache memory, and if said requested data is stored in said cache memory, disabling said main memory means accessing said requested data which is stored in main memory; wherein said main memory means continue to access said requested data from said main memory if said requested data is not stored in said cache memory; and wherein no delay in accessing said main memory is created by said concurrent and parallel access by said cache memory means.
Claim 3
Dependent Claim
24 words
A system as recited in claim 1, wherein said means for accessing data that is stored in said main memory comprises a memory controller.
Claim 4
Dependent Claim
25 words
A system as recited in claim 2, wherein said means for accessing data that may be stored in said cache memory comprises a cache controller.
Claim 5
Dependent Claim
27 words
The computer system of claim 1 wherein said cache memory is accessed by a row address strobe (RAS) signal followed by a column address strobe (CAS) signal.
Claim 6
Dependent Claim
21 words
The computer system of claim 4 wherein said main memory is access by said RAS signal followed by said CAS signal.
Claim 7
Dependent Claim
27 words
The computer system of claim 5 wherein said main memory is accessed by said RAS signal concurrently with said cache memory being accessed by said RAS signal.
Claim 8
Dependent Claim
26 words
The computer system of claim 1 wherein said cache memory means does not duplicate a processor bus interface between the CPU and the main memory means.
Claim 9
Dependent Claim
148 words
A computer system for accessing a main memory and a cache memory in parallel , without cache lookup latency, the computer system comprising: a central processing unit (CPU) for processing data stored in either of said main memory or said cache memory; a main memory controller electrically connected to said CPU and accessible by said CPU for providing data to said CPU that is stored in said main memory; a cache controller electrically connected to said CPU and accessible by said CPU for providing data to said CPU that is stored in said cache memory; means for concurrently retrieving requested data from both said cache memory and said main memory by simultaneously activating both said cache memory controller and said main memory controller; and means for terminating access of said main memory controller upon an occurrence of a successful retrieval of said requested data from said cache memory.
Claim 10
Dependent Claim
148 words
A computer system for accessing a main memory and a cache memory in parallel , without cache lookup latency, the computer system comprising: a central processing unit (CPU) for processing data stored in either of said main memory or said cache memory; a main memory controller electrically connected to said CPU and accessible by said CPU for providing data to said CPU that is stored in said main memory; a cache controller electrically connected to said CPU and accessible by said CPU for providing data to said CPU that is stored in said cache memory; means for concurrently retrieving requested data from both said cache memory and said main memory by simultaneously activating both said cache memory controller and said main memory controller; and means for terminating access of said main memory controller upon an occurrence of a successful retrieval of said requested data from said cache memory.
Claim 11
Dependent Claim
30 words
A system as recited in claim 8, wherein said means for terminating access of said memory controller includes a deasserted miss line interconnecting said cache controller and said memory controller.
Claim 12
Dependent Claim
132 words
A computer system having a main memory, a main memory controller, a cache memory and a cache memory controller, said system comprising: means, electrically connected to both said main memory controller and said cache memory controller, for generating a physical address; means, electrically connected to said generating means, for concurrently applying said physical address to said main memory controller and to said cache memory controller, to thereby retrieve data from said cache memory and said main memory through simultaneous activation of both said cache memory controller and said main memory controller; and means, electrically connected to said cache memory controller and said main memory controller, for terminating the application of said physical address to said main memory controller upon an occurrence of a successful retrieval of said data from said cache memory.
Claim 13
Dependent Claim
132 words
A computer system having a main memory, a main memory controller, a cache memory and a cache memory controller, said system comprising: means, electrically connected to both said main memory controller and said cache memory controller, for generating a physical address; means, electrically connected to said generating means, for concurrently applying said physical address to said main memory controller and to said cache memory controller, to thereby retrieve data from said cache memory and said main memory through simultaneous activation of both said cache memory controller and said main memory controller; and means, electrically connected to said cache memory controller and said main memory controller, for terminating the application of said physical address to said main memory controller upon an occurrence of a successful retrieval of said data from said cache memory.
Claim 14
Dependent Claim
30 words
A system as recited in claim 10, wherein said means for applying said physical address to said main memory controller comprises means for asserting a Control Address Strobe control pulse.
Claim 15
Dependent Claim
37 words
A system as recited in claim 11, wherein said means for terminating the application of said physical address to said main memory controller comprises means for disabling said means for asserting a Control Address Strobe control pulse.
Claim 16
Dependent Claim
24 words
A system as recited in claim 12, further comprising means for detecting a "miss" in said cache memory associated with said cache memory controller.
Claim 17
Dependent Claim
30 words
A system as recited in claim 13, wherein a detection of a "miss" in said cache memory actuates said means for disabling said means for asserting a CAS control signal.
Claim 18
Independent Claim
163 words
A method of accessing data in a computer system including a central processing unit (CPU) electrically connected to a cache memory via a cache memory controller, and electrically connected to a main memory via a main memory controller, wherein both said main memory and said cache memory can store the data, said method comprising the steps of: accessing said cache memory, said cache memory accessing step performed by said CPU; accessing said main memory, said main memory accessing step performed by said CPU, at the same time said cache memory is accessed, to thereby retrieve said data from both said cache memory and said main memory through simultaneous activation by said CPU of both said cache memory controller and said main memory controller coupled to said cache memory and said main memory, respectively; and terminating the access of said main memory, said terminating step performed by said cache controller upon an occurrence of a successful retrieval of said data from said cache memory.
Claim 19
Independent Claim
163 words
A method of accessing data in a computer system including a central processing unit (CPU) electrically connected to a cache memory via a cache memory controller, and electrically connected to a main memory via a main memory controller, wherein both said main memory and said cache memory can store the data, said method comprising the steps of: accessing said cache memory, said cache memory accessing step performed by said CPU; accessing said main memory, said main memory accessing step performed by said CPU, at the same time said cache memory is accessed, to thereby retrieve said data from both said cache memory and said main memory through simultaneous activation by said CPU of both said cache memory controller and said main memory controller coupled to said cache memory and said main memory, respectively; and terminating the access of said main memory, said terminating step performed by said cache controller upon an occurrence of a successful retrieval of said data from said cache memory.
Claim 20
Independent Claim
150 words
A method of accessing data in a computer system including a central processing unit (CPU) electrically connected to a main memory via a main memory controller, and electrically connected to a cache memory via a cache memory controller, wherein both said main memory and said cache memory can store the data, said method comprising the steps of: generating a physical address, said generating step performed by said CPU; concurrently applying said physical address to said main memory controller and said cache memory controller, to thereby retrieve said data from both said cache memory and said main memory through simultaneous activation of both said cache memory controller and said main memory controller; and determining whether or not to terminate application of said physical address to said main memory controller, said determining step performed by said cache controller upon an occurrence of a successful retrieval of said data from said cache memory.
Claim 21
Independent Claim
150 words
A method of accessing data in a computer system including a central processing unit (CPU) electrically connected to a main memory via a main memory controller, and electrically connected to a cache memory via a cache memory controller, wherein both said main memory and said cache memory can store the data, said method comprising the steps of: generating a physical address, said generating step performed by said CPU; concurrently applying said physical address to said main memory controller and said cache memory controller, to thereby retrieve said data from both said cache memory and said main memory through simultaneous activation of both said cache memory controller and said main memory controller; and determining whether or not to terminate application of said physical address to said main memory controller, said determining step performed by said cache controller upon an occurrence of a successful retrieval of said data from said cache memory.
Claim 22
Dependent Claim
36 words
A method as recited in claim 16, further comprising the step of determining whether or not said data corresponding to said generated physical address is located in said cache memory associated with said cache memory controller.
Claim 23
Dependent Claim
34 words
A method as recited in claim 17, wherein a decision to terminate application of said physical address to said main memory follows a determination that desired data was not located in said cache memory.
Claim 24
Dependent Claim
20 words
A method as recited in claim 18, further comprising the optional step of asserting a Control Address Strobe control pulse.
Claim 25
Dependent Claim
35 words
A method as recited in claim 19, wherein said step of asserting a Control Address Strobe control pulse is performed if a decision is made to terminate application of said address to said main memory.
Claim 26
Dependent Claim
39 words
A method as recited in claim 20, wherein said step of asserting a Control Address Strobe control pulse is performed if and only if a decision is made to not terminate application of said address to said main memory.
Claim 27
Dependent Claim
153 words
A computer system having a central processing unit (CPU) electrically connected to a first memory and to a second memory, said computer system comprising: a first controller, electrically connected between said CPU and said first memory, for accessing data stored in said first memory; a second controller, electrically connected between said CPU and said second memory, for accessing data stored in said second memory; address circuitry, electrically connected to both said first controller and to said second controller, for simultaneously providing address signals to both said first controller and to said second controller; and control circuitry, electrically connected to both said first controller and to said second controller, for concurrently retrieving data from both said first memory and said second memory by simultaneously activating both said first controller and said second controller, said first controller disabling said second controller upon an occurrence of a successful retrieval of said data from said first memory.
Claim 28
Dependent Claim
153 words
A computer system having a central processing unit (CPU) electrically connected to a first memory and to a second memory, said computer system comprising: a first controller, electrically connected between said CPU and said first memory, for accessing data stored in said first memory; a second controller, electrically connected between said CPU and said second memory, for accessing data stored in said second memory; address circuitry, electrically connected to both said first controller and to said second controller, for simultaneously providing address signals to both said first controller and to said second controller; and control circuitry, electrically connected to both said first controller and to said second controller, for concurrently retrieving data from both said first memory and said second memory by simultaneously activating both said first controller and said second controller, said first controller disabling said second controller upon an occurrence of a successful retrieval of said data from said first memory.
Claim 29
Dependent Claim
14 words
The computer system of claim 22 wherein said first controller is a cache controller.
Claim 30
Dependent Claim
14 words
The computer system of claim 22 wherein said second controller is a memory controller.
Claim 31
Dependent Claim
18 words
The computer system of claim 22 wherein said address circuitry comprises an address bus and a control bus.
Claim 32
Dependent Claim
29 words
The computer system of claim 22 wherein said selected data is data that is stored at the physical address relating to said address signals provided by said address circuitry.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-27 | 1997-12-27 | 1998-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-27 | 2001-12-27 | 2002-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-27 | 2005-12-27 | 2006-06-28 | $7700.00 | Window Closed / Lapsed |