Computer memory system

Claim 1

In combination a central processor and a computer memory system, said computer memory system including: a relatively slow access relatively large main memory; a relatively fast access relatively small auxiliary memory; a plurality of parallel transfer lines intercoupling said main memory and said auxiliary memory; first control circuitry coupled to the central processor and to the main and auxiliary memories for accessing the auxiliary memory for all words addressed by the central processor which are stored in the auxiliary memory, and for accessing the main memory when a particular addressed work cannot be found in the auxiliary memory, said first control circuitry including storage means for storing the main memory address of all words presently stored in said auxiliary memory, comparator means for simultaneously comparing a desired main memory address received from the central processor against all the main memory addresses stored in said storage means, logic circuitry coupled to said comparator means for converting the desired main memory address into the corresponding auxiliary memory address if a match is made by said comparator means and for accessing the addressed work in said auxiliary memory, and further logic circuitry connected to said comparator means for effectively transferring the particular addressed word and a predetermined number of adjacent words from the main memory to the auxiliary memory along said parallel transfer lines when no match is made by said comparator means.