Integrating imaging systgem having wide dynamic range with sample/hold circuits

Claim 2

An integrating imaging array disposed on a single piece of semiconductor substrate material, including: a plurality of integrating photosensors arranged in an array of rows and columns, each of said photosensors comprising a bipolar phototransistor having a collector connected to a fixed voltage source, an emitter connected to a sense node, and a base connected to one end of a capacitor, the other end of said capacitor connected to a select node; a plurality of row lines, each one of said row lines associated with a different row in said array; each of said row lines connected to the select nodes of all of the integrating photosensors associated with its row; and a plurality of sense lines, each one of said sense lines associated with a different column in said array, each of said sense lines connected to the sense nodes of all of the integrating photosensors associated with its row; a plurality of sense amplifiers, each one of said sense amplifiers associated with a different column of said array, each of said sense amplifiers having an inverting input and an output, said inverting input of each of said sense amplifiers connected to the one of said sense lines associated with its column, each of said sense amplifiers further including a varactor element connected between said inverting input and said output; means for placing a signal on a selected one of said row lines to activate the select nodes of the integrating photosensors associated with said selected one of said row lines; a plurality of sample/hold circuits, each one of said sample/hold circuits associated with a different column of said array, each of said sample/hold circuits having a control input, a data input and a data output, the data input of each of said sample/hold circuits connected to the output of the one of said sense amplifiers associated with its column; and means for selectively activating the control inputs of said sample/hold circuits.

Claim 3

The integrated imaging array of claim 1 wherein said varactor element of each of said sense amplifiers comprises an MOS transistor having its gate connected to said inverting input of said sense amplifier and its source and drain connected to said output of said sense amplifier.

Claim 4

The integrated imaging array of claim 1 wherein said varactor element of each of said sense amplifiers comprises an MOS transistor having its gate connected to said output of said sense amplifier and its source and drain connected to said inverting input of said sense amplifier.

Claim 5

The integrated imaging array of claim 2 wherein each of said sense amplifiers further includes means for selectively connecting its output to its inverting input.

Claim 6

The integrating imaging array of claim 4 wherein said means for selectively connecting comprises an MOS transistor connected between said input node and said output node, said MOS transistor having its gate connected to a balance input node.

Claim 7

The integrated imaging array of claim 1, further including means for adapting said sense amplifier to a known state when none of said rows are selected.

Claim 8

The integrated imaging array of claim 1, further including: means for serially selecting each of said rows in order; and means for serially selecting the outputs of said sample/hold circuits when each of said rows has been selected.

Claim 9

An integrating imaging array disposed on a single piece of semiconductor substrate material, including: a plurality of integrating photosensors arranged in a matrix including a plurality of rows and columns, each of said integrating photosensors including an integrating photosensitive element, a sense node, an enable node, and a semiconductor switch connected between said integrating photosensitive element and said sense node, said semiconductor switch having a control input connected to said enable node; a plurality of row lines, a different one of said row lines associated with each row in said array, each of said row lines connected to the enable nodes of all of said integrating photosensors associated with its row; a plurality of sense, lines, a different one of said sense lines associated with each column in said array, each of said sense lines connected to the sense nodes of all of said integrating photosensors associated with its column; a plurality of sense amplifiers, each one of said sense amplifiers associated with a different column of said array, each of said sense amplifiers having an inverting input and an output, said inverting input of each of said sense amplifiers connected to the one of said sense lines associated with its column, each of said sense amplifiers further including a varactor element connected between said inverting input and said output; means for placing a signal on a selected one of said row lines to activate the select nodes of the integrating photosensors associated with said selected one of said row lines; a plurality of sample/hold circuits, each one of said sample/hold circuits associated with a different column of said array, each of said sample/hold circuits having a control input, a data input and a data output, the data input of each of said sample/hold circuits connected to the one of said sense amplifiers associated with its column; and means for selectively activating the control inputs of said sample/hold circuits.

Claim 10

An integrating imaging array disposed on a single piece of semiconductor substrate material, including: a plurality of integrating photosensors arranged in a matrix including a plurality of rows and columns, each of said integrating photosensors including an integrating photosensitive element, a sense node, an enable node, and a semiconductor switch connected between said integrating photosensitive element and said sense node, said semiconductor switch having a control input connected to said enable node; a plurality of row lines, a different one of said row lines associated with each row in said array, each of said row lines connected to the enable nodes of all of said integrating photosensors associated with its row; a plurality of sense, lines, a different one of said sense lines associated with each column in said array, each of said sense lines connected to the sense nodes of all of said integrating photosensors associated with its column; a plurality of sense amplifiers, each one of said sense amplifiers associated with a different column of said array, each of said sense amplifiers having an inverting input and an output, said inverting input of each of said sense amplifiers connected to the one of said sense lines associated with its column, each of said sense amplifiers further including a varactor element connected between said inverting input and said output; means for placing a signal on a selected one of said row lines to activate the select nodes of the integrating photosensors associated with said selected one of said row lines; a plurality of sample/hold circuits, each one of said sample/hold circuits associated with a different column of said array, each of said sample/hold circuits having a control input, a data input and a data output, the data input of each of said sample/hold circuits connected to the one of said sense amplifiers associated with its column; and means for selectively activating the control inputs of said sample/hold circuits.

Claim 11

The integrated imaging array of claim 8 wherein said varactor element of each of said sense amplifiers comprises an MOS transistor having its gate connected to said inverting input of said sense amplifier and its source and drain connected to said output of said sense amplifier.

Claim 12

The integrated imaging array of claim 8 wherein said varactor element of each of said sense amplifiers comprises an MOS transistor having its gate connected to said output of said sense amplifier and its source and drain connected to said inverting input of said sense amplifier.

Claim 13

The integrated imaging array of claim 8 wherein each of said sense amplifiers further includes means for selectively connecting its output to its inverting input.

Claim 14

The integrating imaging array of claim 11 wherein said means for selectively connecting comprises an MOS transistor connected between said input node and said output node, said MOS transistor having its gate connected to a balance input node.

Claim 15

The integrated imaging array of claim 8, further including means for adapting said amplifiers to a known state when none of said rows are selected.

Claim 16

The integrating imaging array of claim 8 wherein each of said integrating photosensors comprises a bipolar phototransistor having a base, an emitter, and a collector, said collector connected to a voltage source, and said emitter connected to said semiconductor switch.

Claim 17

The integrating imaging array of claim 8 wherein each of said integrating photosensors comprises a photodiode.

Claim 18

The integrated imaging array of claim 8, further including: means for serially selecting each of said rows in order; and means for serially selecting the outputs of said sample/hold circuits when each of said rows has been selected.

Claim 19

An integrating imaging array disposed on a single piece of semiconductor substrate material of a first conductivity type, including: a plurality of integrating photosensors disposed in a well of a second conductivity type opposite to said first conductivity type, said plurality of integrating photosensors arranged in a matrix including a plurality of rows and columns, each of said integrating photosensors comprising a bipolar phototransistor having a collector region formed by said well, a base region formed from a region of said first conductivity type disposed in said well, and an emitter region formed from a region of said second conductivity type disposed in said base region, said well connected to a voltage source; a capacitor dielectric layer formed over said base regions of said bipolar phototransistors; a plurality of row lines, a different one of said row lines associated with each row in said array, each of said row lines comprising a conductive strip disposed over said capacitor dielectric layer in a region lying over a portion of the base regions of the ones of said bipolar phototransistors in the one of said rows with which it is associated, each of said strips including a plurality of first-sized apertures therein, each of said apertures extending through said capacitor dielectric and substantially self aligned with the emitter region of a different one of said bipolar phototransistors, said strips, said capacitor dielectric layer and said base regions acting to capacitively couple said base regions of the ones of said bipolar phototransistors associated with each of said corresponding rows to the unique one of said row lines associated therewith; an insulating layer covering said polysilicon strips, said insulating layer including a plurality of second-sized contact apertures therein, said second-sized contact apertures substantially aligned with said first-sized apertures and extending through said insulating layer to said emitter regions, said second-sized contact apertures being sized smaller than said first-sized apertures so as to prevent contact to said conductive strips; a plurality of conductive sense lines disposed over said second insulating layer and disposed in a direction generally orthogonal to said conductive strips, a different one of said sense lines associated with each of said columns in said array, the emitters of all of the ones of said integrating photosensors in each column connected to the one of said sense lines with which that column is associated through ones of said second-sized contact apertures; a plurality of sense amplifiers, each one of said sense amplifiers associated with a different column of said array, each of said sense amplifiers having an inverting input and an output, said inverting input of each of said sense amplifiers connected to the one of said sense lines associated with its column, each of said sense amplifiers further including a varactor element connected between said inverting input and said output; means for placing a signal on a selected one of said row lines to forward bias the base regions of the integrating photosensors associated with said selected one of said row lines; a plurality of sample/hold circuits, each one of said sample/hold circuits associated with a different column of said array, each of said sample/hold circuits having a control input, a data input and a data output, the data input of each of said sample/hold circuits connected to the output of the one of said sense amplifiers associated with its column; and means for selectively activating the control inputs of said sample/hold circuits.

Claim 20

An integrating imaging array disposed on a single piece of semiconductor substrate material of a first conductivity type, including: a plurality of integrating photosensors disposed in a well of a second conductivity type opposite to said first conductivity type, said plurality of integrating photosensors arranged in a matrix including a plurality of rows and columns, each of said integrating photosensors comprising a bipolar phototransistor having a collector region formed by said well, a base region formed from a region of said first conductivity type disposed in said well, and an emitter region formed from a region of said second conductivity type disposed in said base region, said well connected to a voltage source; a capacitor dielectric layer formed over said base regions of said bipolar phototransistors; a plurality of row lines, a different one of said row lines associated with each row in said array, each of said row lines comprising a conductive strip disposed over said capacitor dielectric layer in a region lying over a portion of the base regions of the ones of said bipolar phototransistors in the one of said rows with which it is associated, each of said strips including a plurality of first-sized apertures therein, each of said apertures extending through said capacitor dielectric and substantially self aligned with the emitter region of a different one of said bipolar phototransistors, said strips, said capacitor dielectric layer and said base regions acting to capacitively couple said base regions of the ones of said bipolar phototransistors associated with each of said corresponding rows to the unique one of said row lines associated therewith; an insulating layer covering said polysilicon strips, said insulating layer including a plurality of second-sized contact apertures therein, said second-sized contact apertures substantially aligned with said first-sized apertures and extending through said insulating layer to said emitter regions, said second-sized contact apertures being sized smaller than said first-sized apertures so as to prevent contact to said conductive strips; a plurality of conductive sense lines disposed over said second insulating layer and disposed in a direction generally orthogonal to said conductive strips, a different one of said sense lines associated with each of said columns in said array, the emitters of all of the ones of said integrating photosensors in each column connected to the one of said sense lines with which that column is associated through ones of said second-sized contact apertures; a plurality of sense amplifiers, each one of said sense amplifiers associated with a different column of said array, each of said sense amplifiers having an inverting input and an output, said inverting input of each of said sense amplifiers connected to the one of said sense lines associated with its column, each of said sense amplifiers further including a varactor element connected between said inverting input and said output; means for placing a signal on a selected one of said row lines to forward bias the base regions of the integrating photosensors associated with said selected one of said row lines; a plurality of sample/hold circuits, each one of said sample/hold circuits associated with a different column of said array, each of said sample/hold circuits having a control input, a data input and a data output, the data input of each of said sample/hold circuits connected to the output of the one of said sense amplifiers associated with its column; and means for selectively activating the control inputs of said sample/hold circuits.

Claim 21

The integrated imaging array of claim 17 wherein said varactor element of each of said sense amplifiers comprises an MOS transistor having its gate connected to said inverting input of said sense amplifier and its source and drain connected to said output of said sense amplifier.

Claim 22

The integrated imaging array of claim 17 wherein said varactor element of each of said sense amplifiers comprises an MOS transistor having its gate connected to said output of said sense amplifier and its source and drain connected to said inverting input of said sense amplifier.

Claim 23

The integrated imaging array of claim 17 wherein each of said sense amplifiers further includes means for selectively connecting its output to its inverting input.

Claim 24

The integrating imaging array of claim 20 wherein said means for selectively connecting comprises an MOS transistor connected between said input node and said output node, said MOS transistor having its gate connected to a balance input node.

Claim 25

The integrated imaging array of claim 17, further including means for adapting said amplifier to a known state when none of said rows are selected.

Claim 26

The integrated imaging array of claim 17, further including: means for serially selecting each of said rows in order; and means for serially selecting the outputs of said sample/hold circuits when each of said rows has been selected.

Claim 27

An integrating imaging array disposed on a single piece of semiconductor substrate material of a first conductivity type, including: a plurality of integrating photosensors disposed in said semiconductor substrate material, said plurality of integrating photosensors arranged in a matrix including a plurality of rows and columns, each of said integrating photosensors comprising a bipolar phototransistor having a collector region formed by said semiconductor substrate material, a base region formed from a region of a second conductivity type opposite to that of said first conductivity type disposed in said semiconductor substrate material, and an emitter region formed from a region of said first conductivity type disposed in said base region, said semiconductor substrate material connected to a voltage source; a capacitor dielectric layer formed over said base regions of said bipolar phototransistors; a plurality of row lines, a different one of said row lines associated with each row in said array, each of said row lines comprising a conductive strip disposed over said capacitor dielectric layer in a region lying over a portion of the base regions of the ones of said bipolar phototransistors in the one of said rows with which it is associated, each of said strips including a plurality of first-sized apertures therein, each of said apertures extending through said capacitor dielectric and substantially self aligned with the emitter region of a different one of said bipolar phototransistors, said strips, said capacitor dielectric layer and said base regions acting to capacitively couple said base regions of the ones of said bipolar phototransistors associated with each of said corresponding rows to the unique one of said row lines associated therewith; an insulating layer covering said polysilicon strips, said insulating layer including a plurality of second-sized contact apertures therein, said second-sized contact apertures substantially aligned with said first-sized apertures and extending through said insulating layer to said emitter regions, said second-sized contact apertures being sized smaller than said first-sized apertures so as to prevent contact to said conductive strips; a plurality of conductive sense lines disposed over said second insulating layer and disposed in a direction generally orthogonal to said conductive strips, a different one of said sense lines associated with each of said columns in said array, the emitters of all of the ones of said integrating photosensors in each column connected to the one of said sense lines with which that column is associated through ones of said second-sized contact apertures; a plurality of sense amplifiers, each one of said sense amplifiers associated with a different column of said array, each of said sense amplifiers having an inverting input and an output, said inverting input of each of said sense amplifiers connected to the one of said sense lines associated with its column, each of said sense amplifiers further including a varactor element connected between said inverting input and said output; means for placing a signal on a selected one of said row lines to forward bias the base regions of the integrating photosensors associated with said selected one of said row lines; a plurality of sample/hold circuits, each one of said sample/hold circuits associated with a different column of said array, each of said sample/hold circuits having a control input, a data input and a data output, the data input of each of said sample/hold circuits connected to the output of the one of said sense amplifiers associated with its column; and means for selectively activating the control inputs of said sample/hold circuits.

Claim 28

An integrating imaging array disposed on a single piece of semiconductor substrate material of a first conductivity type, including: a plurality of integrating photosensors disposed in said semiconductor substrate material, said plurality of integrating photosensors arranged in a matrix including a plurality of rows and columns, each of said integrating photosensors comprising a bipolar phototransistor having a collector region formed by said semiconductor substrate material, a base region formed from a region of a second conductivity type opposite to that of said first conductivity type disposed in said semiconductor substrate material, and an emitter region formed from a region of said first conductivity type disposed in said base region, said semiconductor substrate material connected to a voltage source; a capacitor dielectric layer formed over said base regions of said bipolar phototransistors; a plurality of row lines, a different one of said row lines associated with each row in said array, each of said row lines comprising a conductive strip disposed over said capacitor dielectric layer in a region lying over a portion of the base regions of the ones of said bipolar phototransistors in the one of said rows with which it is associated, each of said strips including a plurality of first-sized apertures therein, each of said apertures extending through said capacitor dielectric and substantially self aligned with the emitter region of a different one of said bipolar phototransistors, said strips, said capacitor dielectric layer and said base regions acting to capacitively couple said base regions of the ones of said bipolar phototransistors associated with each of said corresponding rows to the unique one of said row lines associated therewith; an insulating layer covering said polysilicon strips, said insulating layer including a plurality of second-sized contact apertures therein, said second-sized contact apertures substantially aligned with said first-sized apertures and extending through said insulating layer to said emitter regions, said second-sized contact apertures being sized smaller than said first-sized apertures so as to prevent contact to said conductive strips; a plurality of conductive sense lines disposed over said second insulating layer and disposed in a direction generally orthogonal to said conductive strips, a different one of said sense lines associated with each of said columns in said array, the emitters of all of the ones of said integrating photosensors in each column connected to the one of said sense lines with which that column is associated through ones of said second-sized contact apertures; a plurality of sense amplifiers, each one of said sense amplifiers associated with a different column of said array, each of said sense amplifiers having an inverting input and an output, said inverting input of each of said sense amplifiers connected to the one of said sense lines associated with its column, each of said sense amplifiers further including a varactor element connected between said inverting input and said output; means for placing a signal on a selected one of said row lines to forward bias the base regions of the integrating photosensors associated with said selected one of said row lines; a plurality of sample/hold circuits, each one of said sample/hold circuits associated with a different column of said array, each of said sample/hold circuits having a control input, a data input and a data output, the data input of each of said sample/hold circuits connected to the output of the one of said sense amplifiers associated with its column; and means for selectively activating the control inputs of said sample/hold circuits.

Claim 29

The integrated imaging array of claim 24 wherein said varactor element of each of said sense amplifiers comprises an MOS transistor having its gate connected to said inverting input of said sense amplifier and its source and drain connected to said output of said sense amplifier.

Claim 30

The integrated imaging array of claim 24 wherein said varactor element of each of said sense amplifiers comprises an MOS transistor having its gate connected to said output of said sense amplifier and its source and drain connected to said inverting input of said sense amplifier.

Claim 31

The integrated imaging array of claim 24 wherein each of said sense amplifiers further includes means for selectively connecting its output to its inverting input.

Claim 32

The integrating imaging array of claim 27 wherein said means for selectively connecting comprises an MOS transistor connected between said input node and said output node, said MOS transistor having its gate connected to a balance input node.

Claim 33

The integrated imaging array of claim 24, further including means for adapting said amplifier to a known state when none of said rows are selected.

Claim 34

The integrated imaging array of claim 24, further including: means for serially selecting each of said rows in order; and means for serially selecting the outputs of said sample/hold circuits when each of said rows has been selected.