US4783694A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated bipolar-MOS semiconductor device with common collector and drain
Assignee: Motorola Solutions Inc
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Filing: 1984-03-16
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Granted: 1988-11-08
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Expires: 2004-03-16
Abstract
Abstract The safe operating area can be increased and the die area can be decreased for a monolithic Darlington circuit employing an MOS input transistor and bipolar output transistor by subdividing the bipolar transistor into a multiplicity of rectangular spaced apart bipolar device regions, each of which is surrounded by an annular shaped MOS device region. The source and channel of the MOS devices are formed in an extension of the base of the bipolar devices. The substrate serves as a common collector for all the bipolar device regions and as a common drain for all the MOS device regions. The gate electrode, which runs over the interstices between the parallel spaced apart bipolar device areas is covered by an insulator so that the emitter metallization may extend substantially over the entire upper surface of the die. A more compact layout and better thermal coupling between the MOS and bipolar devices are obtained. These features reduce the total die area and improve the thermal stability of the circuit.
Inventors
- 👤 Perry L. Merrill
- 👤 Rodney R. Stoltenburg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:33
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/101; H10D84/121; H10D84/125; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D62/127; H10D84/40; H10D84/401; H10D84/403; H10D84/406
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
117 words
A semiconductor device having a surface, comprising: a bipolar transistor having emitter, base, and collector regions, wherein said emitter and base regions extend to said surface of said device; an emitter electrode extending over a first portion of said surface and contacting said emitter region and a first portion of said first base region; and an MOS transistor, substantially surrounding said bipolar transistor, and having source, drain, and channel regions extending to said surface, and having a gate electrode extending above said channel region, wherein said source and channel regions are formed in a second portion of said base region extending from the periphery of said emitter region and wherein said drain and collector regions are common.
Claim 2
Dependent Claim
117 words
A semiconductor device having a surface, comprising: a bipolar transistor having emitter, base, and collector regions, wherein said emitter and base regions extend to said surface of said device; an emitter electrode extending over a first portion of said surface and contacting said emitter region and a first portion of said first base region; and an MOS transistor, substantially surrounding said bipolar transistor, and having source, drain, and channel regions extending to said surface, and having a gate electrode extending above said channel region, wherein said source and channel regions are formed in a second portion of said base region extending from the periphery of said emitter region and wherein said drain and collector regions are common.
Claim 3
Dependent Claim
39 words
The device of claim 1 further comprising shorting means at a junction between said source and base regions, and integrated resistor means in said base region extending from said shorting means to said first portion of said base region.
Claim 4
Dependent Claim
20 words
The device of claim 2 wherein said first portion of said base region is laterally surrounded by said emitter region.
Claim 5
Dependent Claim
22 words
The device of claim 2 wherein said shorting means is insulated from said emitter region, said emitter electrode, and said gate electrode.
Claim 6
Dependent Claim
43 words
The device of claim 1 further comprising at least two separate parallel spaced-apart emitter regions and at least two separate annular source regions arranged so that each of said separate spaced-apart emitter regions is surrounded by one of said separate annular source regions.
Claim 7
Dependent Claim
137 words
The device of claim 1 further comprising at least first and second elongated parallel spaced-apart base regions and first and second elongated parallel spaced-apart emitter regions, wherein said first and second elongated parallel spaced-apart base regions have an elongated gap therebetween, and wherein said first and second elongated spaced-apart base regions laterally enclose, respectively, said first and second elongated emitter regions, and wherein the portions of said first and second elongated spaced-apart base regions adjacent said elongated gap contain, respectively, first and second elongated source regions separated from said gap by first and second elongated channel regions lying in said first and second elongated spaced-apart base regions between said first and second elongated source regions and said gap, and wherein a common elongated gate electrode overlies said first and second elongated channel regions and said elongated gap.
Claim 8
Dependent Claim
24 words
The device of claim 6 further comprising an insulator overlying a portion of said gate electrode, and wherein said emitter electrode overlies said insulator.
Claim 9
Dependent Claim
21 words
The device of claim 7 wherein said emitter electrode substantially covers the portion of said gate electrode that overlies said gap.
Claim 10
Dependent Claim
67 words
The device of claim 6 wherein said emitter electrode extends from said first elongated emitter region, across the portions of said first elongated base, source, and channel regions adjacent said elongated gap, across the portion of said elongated gate region covering said elongated gap, across the portions of said second elongated channel, source, and base regions adjacent said elongated gap, and to said second elongated emitter region.
References Cited (Backward Citations)
US3702947A
Cited
US3821780A
Cited
US3813588A
Cited
US3913213A
Cited
US4072975A
Cited
US4145700A
Cited
JPS53142184A
Cited
US4198693A
Cited
US4288807A
Cited
US4206469A
Cited
US4199774A
Cited
US4329705A
Cited
US4366522A
Cited
JPS5765269A
Cited
US4430663A
Cited
GB2097585A
Cited
US4441117A
Cited
JPS5892263A
Cited
DE3210353A1
Cited
JPS58165374A
Cited
US4489341A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-08 | 1992-05-09 | 1992-11-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-08 | 1996-05-09 | 1996-11-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-08 | 2000-05-09 | 2000-11-08 | $7700.00 | Window Closed / Lapsed |