Semiconductor memory device and the fabrication method thereof

Claim 1

A method for manufacturing a semiconductor memory device having a cell array area and peripheral circuit area comprising the steps of: forming a field oxide film on a first conductivity type semiconductor substrate; laminating and etching a gate oxide film and a first conductive layer on the whole surface of said semiconductor substrate, thereby forming gate electrodes in said cell array and peripheral circuit area; doping a second conductivity type impurity on the whole surface of the semiconductor substrate on which said gate electrodes have been formed, thereby forming a first impurity region; forming a spacer material, on the whole surface of the semiconductor substrate on which said first impurity diffusion region has been formed; coating a photoresist layer on the whole surface of the semiconductor substrate on which said spacer material has been formed and removing the photoresist layer on the peripheral circuit area by a photolithographic process; removing said spacer material exposed through said photoresist layer by an anisotropic etching to form spacers on the side walls of the gate electrodes in said peripheral circuit area and then removing the remaining photoresist; and doping a second conductivity type impurity using said spacers as a mask, thereby forming a second impurity diffusion region in said peripheral circuit area.

Claim 2

A method for manufacturing a semiconductor memory device having a cell array area and peripheral circuit area comprising the steps of: forming a field oxide film on a first conductivity type semiconductor substrate; laminating and etching a gate oxide film and a first conductive layer on the whole surface of said semiconductor substrate, thereby forming gate electrodes in said cell array and peripheral circuit area; doping a second conductivity type impurity on the whole surface of the semiconductor substrate on which said gate electrodes have been formed, thereby forming a first impurity region; forming a spacer material, on the whole surface of the semiconductor substrate on which said first impurity diffusion region has been formed; coating a photoresist layer on the whole surface of the semiconductor substrate on which said spacer material has been formed and removing the photoresist layer on the peripheral circuit area by a photolithographic process; removing said spacer material exposed through said photoresist layer by an anisotropic etching to form spacers on the side walls of the gate electrodes in said peripheral circuit area and then removing the remaining photoresist; and doping a second conductivity type impurity using said spacers as a mask, thereby forming a second impurity diffusion region in said peripheral circuit area.