Single-chip microcomputer including non-volatile memory elements

Claim 2

A single-chip microcomputer comprising: a data bus transferring data or programs of a predetermined bit width; an address bus transferring an address in an address space (map) corresponding to the bit width; a CPU coupled to said data bus and said address bus for processing program data; a ROM coupled to said data bus and said address bus and storing programs for operating the single-chip microcomputer; a logic circuit coupled to said data bus and said address bus, having a plurality of non-volatile memory elements, and having a programmable variable logical construction, the programmable variable logical construction being programmed by electrically writing information into said plurality of non-volatile memory elements; and one or more ports coupled to said data bus and said address bus inputting or outputting at least one of the data, program and address to an external device; wherein writing and erasing operations of said plurality of non-volatile memory elements in said logic circuit from the external device, are executed by designating an allocated address in said address space (map) for said logic circuit.

Claim 3

The single-chip microcomputer according to claim 1, further comprising: an input/output (I/O) port coupled to said data bus, and an input selector, and wherein said logic circuit further comprises a logical product execution unit that includes an input and a logical sum execution unit, and wherein said input selector is coupled between the input of said logical product execution unit and said address bus as well as said data bus.

Claim 4

The single-chip microcomputer according to claim 2, further comprising output selection means having an input, a first output coupled to the data bus, and a second output coupled to the input/output port means, and wherein said logical sum execution unit has an output coupled to the input of the output selection means.

Claim 5

The single-chip microcomputer according to claim 1, further comprising an exterior, wherein said logic circuit controls data communications between said CPU and the exterior of said single-chip microcomputer.

Claim 6

The single-chip microcomputer according to claim 1, further comprising: an exterior; a first signal transmitter coupled between said address bus as well as said data bus and said CPU; a second signal transmitter coupled between said address bus as well as said data bus and said ROM; a third signal transmitter coupled between said address bus as well as said data bus and said logic circuit; a fourth signal transmitter coupled between the exterior of said chip and said address bus as well as said data bus; and a control signal generator producing a plurality of internal control signals so as to suspend signal transmission functions of any of said first, second, third and fourth signal transmitters in response to external control signals from outside said single-chip microcomputer.

Claim 7

The single-chip microcomputer according to claim 1, wherein said logic circuit further comprises an address space, and said CPU further comprises a micro-ROM storing microprograms and having a plurality of addresses being located in said address space of the logic circuit.

Claim 8

A semiconductor integrated circuit wherein a function circuit block which generates an output signal in response to an input signal is built in a chip comprising: a data bus transferring data or programs of a predetermined bit width; an address bus transferring an address in an address space (map) corresponding to the bit width; a CPU coupled to said data bus and said address bus for processing program data; a ROM coupled to said data bus and said address bus and storing programs for operating said semiconductor integrated circuit; a control circuit block controlling an operation of said semiconductor integrated circuit associated with an operation of said function circuit block, wherein said control circuit block further comprises a logic circuit coupled to said data bus and said address bus, having a plurality of electrically-programmable non volatile semiconductor memory elements, and having a programmable variable logical construction, the programmable variable logical construction being programmed by electrically writing information into said plurality of non volatile semiconductor memory elements; and one or more ports coupled to said data bus and said address bus inputting or outputting at least one of the data, program and address to an external device; wherein writing and erasing operations of said plurality of non-volatile memory elements in said logic circuit from the external device, are executed by designating an allocated address in said address space (map) for said logic circuit.

Claim 9

A semiconductor integrated circuit wherein a function circuit block which generates an output signal in response to an input signal is built in a chip comprising: a data bus transferring data or programs of a predetermined bit width; an address bus transferring an address in an address space (map) corresponding to the bit width; a CPU coupled to said data bus and said address bus for processing program data; a ROM coupled to said data bus and said address bus and storing programs for operating said semiconductor integrated circuit; a control circuit block controlling an operation of said semiconductor integrated circuit associated with an operation of said function circuit block, wherein said control circuit block further comprises a logic circuit coupled to said data bus and said address bus, having a plurality of electrically-programmable non volatile semiconductor memory elements, and having a programmable variable logical construction, the programmable variable logical construction being programmed by electrically writing information into said plurality of non volatile semiconductor memory elements; and one or more ports coupled to said data bus and said address bus inputting or outputting at least one of the data, program and address to an external device; wherein writing and erasing operations of said plurality of non-volatile memory elements in said logic circuit from the external device, are executed by designating an allocated address in said address space (map) for said logic circuit.

Claim 10

The semiconductor integrated circuit according to claim 7, wherein said semiconductor integrated circuit further comprises a single chip microcomputer, said function circuit block further comprises a CPU, and said logic circuit further comprises a programmable variable logical construction so that logical functions of said logic circuit may be established by electrically writing data into said plurality of electrically-programmable non volatile semiconductor memory elements.

Claim 11

A single chip microcomputer comprising: a data bus transferring data or programs of a predetermined bit width; an address bus transferring an address in an address space (map) corresponding to the bit width; a CPU coupled to said data bus and said address bus for processing program data; a RAM coupled to said data bus and said address bus and storing data; a ROM coupled to said data bus and said address bus and storing programs for operating the single-chip microcomputer; a logic circuit coupled to said data bus and said address bus, and having a programmable variable logical construction, the programmable variable logical construction being programmed by electrically writing information into a plurality of non volatile memory elements; and one or more ports coupled to said data bus and said address bus inputting or outputting at least one of the data, program and address to an external device; wherein writing and erasing operations of said plurality of non-volatile memory elements in said logic circuit from the external device, are executed by designating an allocated address in said address space (map) for said logic circuit.

Claim 12

A single chip microcomputer comprising: a data bus transferring data or programs of a predetermined bit width; an address bus transferring an address in an address space (map) corresponding to the bit width; a CPU coupled to said data bus and said address bus for processing program data; a RAM coupled to said data bus and said address bus and storing data; a ROM coupled to said data bus and said address bus and storing programs for operating the single-chip microcomputer; a logic circuit coupled to said data bus and said address bus, and having a programmable variable logical construction, the programmable variable logical construction being programmed by electrically writing information into a plurality of non volatile memory elements; and one or more ports coupled to said data bus and said address bus inputting or outputting at least one of the data, program and address to an external device; wherein writing and erasing operations of said plurality of non-volatile memory elements in said logic circuit from the external device, are executed by designating an allocated address in said address space (map) for said logic circuit.

Claim 13

A single-chip microcomputer comprising: a data bus transferring data or programs of a predetermined bit width; an address bus transferring an address in an address space (map) corresponding to the bit width; a CPU coupled to said data bus and said address bus for processing program data; a logic circuit coupled to said data bus and said address bus having a plurality of non-volatile memory elements, and having a programmable variable logical construction, the programmable variable logical construction being programmed by electrically writing information into said plurality of non-volatile memory elements; and one or more ports coupled to said data bus and said address bus inputting or outputting at least one of the data, program and address to an external device; wherein writing and erasing operations of said plurality of non-volatile memory elements in said logic circuit from the external device, are executed by designating an allocated address in said address space (map) for said logic circuit.

Claim 14

A single-chip microcomputer comprising: a data bus transferring data or programs of a predetermined bit width; an address bus transferring an address in an address space (map) corresponding to the bit width; a CPU coupled to said data bus and said address bus for processing program data; a logic circuit coupled to said data bus and said address bus having a plurality of non-volatile memory elements, and having a programmable variable logical construction, the programmable variable logical construction being programmed by electrically writing information into said plurality of non-volatile memory elements; and one or more ports coupled to said data bus and said address bus inputting or outputting at least one of the data, program and address to an external device; wherein writing and erasing operations of said plurality of non-volatile memory elements in said logic circuit from the external device, are executed by designating an allocated address in said address space (map) for said logic circuit.

Claim 15

A data processing method which employs a single-chip microcomputer which comprises a CPU, a ROM, a logic circuit having a programmable variable logical construction, an address and data bus, both of which are coupled to said CPU, said ROM, and said logic circuit, wherein said CPU, said ROM, and said logic circuit have adjacent address spaces, said method comprising the steps of: a) electrically writing first data into a plurality of memory elements of the logic circuit to form the programmable variable logical construction; b) reading out the first data electrically written in step a); c) testing the first data from step b) to determine whether or not the data has been normally written; and d) causing the single-chip microcomputer to execute step a) for a second data when a result of step c) is normal.

Claim 16

A data processing method which employs a single-chip microcomputer which comprises a CPU, a ROM, a logic circuit having a programmable variable logical construction, an address and data bus, both of which are coupled to said CPU, said ROM, and said logic circuit, wherein said CPU, said ROM, and said logic circuit have adjacent address spaces, said method comprising the steps of: a) electrically writing first data into a plurality of memory elements of the logic circuit to form the programmable variable logical construction; b) reading out the first data electrically written in step a); c) testing the first data from step b) to determine whether or not the data has been normally written; and d) causing the single-chip microcomputer to execute step a) for a second data when a result of step c) is normal.

Claim 17

A signal processing method which employs a semiconductor integrated circuit which comprises a function circuit block generating an output signal in response to an input signal, and a control circuit block controlling an operation of the semiconductor integrated circuit associated with an operation of the function circuit and including a logic circuit having a plurality of electrically-programmable non volatile memory elements, the method comprising the steps of: a) electrically writing a first data into the plurality of electrically-programmable non volatile memory elements of said logic circuit; b) reading out the first data electrically written in step a); c) testing the first data from step b) to determine whether or not the first data has been normally written; and d) causing said semiconductor integrated circuit to execute step a) for a second data when a result of step c) is normal.

Claim 18

A signal processing method which employs a semiconductor integrated circuit which comprises a function circuit block generating an output signal in response to an input signal, and a control circuit block controlling an operation of the semiconductor integrated circuit associated with an operation of the function circuit and including a logic circuit having a plurality of electrically-programmable non volatile memory elements, the method comprising the steps of: a) electrically writing a first data into the plurality of electrically-programmable non volatile memory elements of said logic circuit; b) reading out the first data electrically written in step a); c) testing the first data from step b) to determine whether or not the first data has been normally written; and d) causing said semiconductor integrated circuit to execute step a) for a second data when a result of step c) is normal.