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US5321655A
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US
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1993-08-24
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Granted: 1994-06-14
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Expires: 2013-08-24
Abstract
Abstract There is disclosed a semiconductor memory device comprising memory cells (M11 to Mnn) for storing binary data, and first reference cells (DM11 to Dm1) and second reference cells (DM12 to DMm2) corresponding to respective two storage states of the memory cell, to make comparisons between the storage state of the memory cell and the storage states of the both reference cells at first and second sense amplifiers (1, 2) to compare outputs from the both sense amplifiers at the third sense amplifier (3) to thereby detect storage data of the memory cell. Thus, there can be provided a high speed memory device which has a less number of memory cells and of a high integration structure, and which has a little possibility of an erroneous operation in reading.
Inventors
- 👤 Hiroshi Iwahashi
- 👤 Hiroto Nakai
- 👤 Kazuhisa Kanazawa
- 👤 Isao Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:12
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/84; G11C29/842; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28; G11C16/32; G11C7/00; G11C7/14
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
215 words
A semiconductor memory device comprising: bit lines, word lines, a memory cell array including memory cells arranged on the intersecting points of said bit lines and said word lines, a auxiliary memory cell array provided in association with said memory cell array, programming means for storing that there are defective cells in said memory cell array, select means wherein when there is any defective cell in said memory cell array, said select means responds to an output from said programming means to select a auxiliary memory cell from said auxiliary memory cell array in place of said defective cell, a reference bit line to which the drain of a reference cell equivalent to said memory cell is connected, a reference potential being produced therefrom, a sense amplifier for comparing a voltage appearing on said bit line with a voltage appearing on said reference bit line to read out data of a selected memory cell, and equalizing means for equalizing said bit line and said reference bit line for a predetermined time at the time of data read operation, whereby when there is any defective cell in said memory cell, an equalization time by said equalizing means is set to a value longer than said predetermined time in response to an output of said programming means.
Claim 2
Dependent Claim
215 words
A semiconductor memory device comprising: bit lines, word lines, a memory cell array including memory cells arranged on the intersecting points of said bit lines and said word lines, a auxiliary memory cell array provided in association with said memory cell array, programming means for storing that there are defective cells in said memory cell array, select means wherein when there is any defective cell in said memory cell array, said select means responds to an output from said programming means to select a auxiliary memory cell from said auxiliary memory cell array in place of said defective cell, a reference bit line to which the drain of a reference cell equivalent to said memory cell is connected, a reference potential being produced therefrom, a sense amplifier for comparing a voltage appearing on said bit line with a voltage appearing on said reference bit line to read out data of a selected memory cell, and equalizing means for equalizing said bit line and said reference bit line for a predetermined time at the time of data read operation, whereby when there is any defective cell in said memory cell, an equalization time by said equalizing means is set to a value longer than said predetermined time in response to an output of said programming means.
Claim 3
Dependent Claim
114 words
A semiconductor memory device as set forth in claim 1, wherein said equalizing means comprises: an equalizing transistor connected between said bit line and said reference bit line, and a delay circuit wherein when an output signal from said programming means is at a first logic level, said delay circuit outputs an equalizing pulse signal for controlling ON/OFF control of said equalizing transistors having a first width at the time of data read operation, while when an output signal from said programming means is at a second logic level, said delay circuit outputs said equalizing pulse signal having a pulse width longer than said first pulse width at the time of data read operation.
Claim 4
Dependent Claim
72 words
A semiconductor memory device as set forth in claim 2, wherein said delay circuit comprises: an inverter, a first MOS transistor connected between said inverter and a power supply, the gate electrode thereof being connected to an input of said inverter, and a second MOS transistor of which gate electrode is connected to the output of said programming means, said second MOS transistor being connected in parallel with said first MOS transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-13 | 1997-12-13 | 1998-06-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-13 | 2001-12-13 | 2002-06-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-13 | 2005-12-13 | 2006-06-14 | $7700.00 | Window Closed / Lapsed |