US5319260A
Expired / Lapsed
US
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Apparatus and method to prevent the disturbance of a quiescent output buffer caused by ground bounce or by power bounce induced by neighboring active output buffers
Assignee: Standard Microsystems LLC
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Filing: 1992-10-20
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Granted: 1994-06-07
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Expires: 2012-10-20
Abstract
Abstract A CMOS device having many output channels at least one of which channel includes a first pair of pull-up/pull-down of transistors between a "noisy Vcc and noisy ground", a second pair of pull-up/pull-down of transistors between a "quiet Vcc and quiet ground", and logic to switch the transistor pairs such that initial switching of an output is powered by the noisy Vcc and ground, and maintenance of an output state is powered by the quiet Vcc and ground. Quiescent channels are decoupled from active channels and will hold their assigned output levels.
Inventors
- 👤 Frank M. Wanlass
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:51
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/16; H03K17/161; H03K17/165; H03K17/166; H03K17/167
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
160 words
A buffer with a single input, comprising: a first pull-up/pull-down transistor pair adapted for connection between a first ground reference and a first Vcc supply, the first pull-up/pull-down transistor pair having means for driving an output of the buffer; a pair of diodes each diode in series with each transistor of the first pull-up/pull-down transistor pair and in series with the output of the buffer; a second pull-up/pull-down transistor pair adapted for connection between a second ground reference which is isolated from said first ground reference and a second Vcc supply which is isolated from said first Vcc supply, the second pull-up/pull-down transistor pair having means for driving said buffer output; and a logic network connected to an input of the buffer and with means to control the first and second pull-up/pull-down transistor pairs such that the first pull-up/pull-down transistor pair initially switches said buffer output from high-to-low and low-to-high, the second pull-up/pull-down transistor pair thereafter clamping said buffer output.
Claim 2
Dependent Claim
160 words
A buffer with a single input, comprising: a first pull-up/pull-down transistor pair adapted for connection between a first ground reference and a first Vcc supply, the first pull-up/pull-down transistor pair having means for driving an output of the buffer; a pair of diodes each diode in series with each transistor of the first pull-up/pull-down transistor pair and in series with the output of the buffer; a second pull-up/pull-down transistor pair adapted for connection between a second ground reference which is isolated from said first ground reference and a second Vcc supply which is isolated from said first Vcc supply, the second pull-up/pull-down transistor pair having means for driving said buffer output; and a logic network connected to an input of the buffer and with means to control the first and second pull-up/pull-down transistor pairs such that the first pull-up/pull-down transistor pair initially switches said buffer output from high-to-low and low-to-high, the second pull-up/pull-down transistor pair thereafter clamping said buffer output.
Claim 3
Dependent Claim
13 words
The buffer of claim 1, wherein: the pair of diodes comprise Schottky diodes.
Claim 4
Dependent Claim
270 words
A p-well process type integrated circuit having a plurality of buffers, each buffer comprising: a first pull-up/pull-down transistor pair for connection between a first ground reference and a first Vcc supply, the first pull-up/pull-down transistor pair coupled for driving an output terminal, the first pull-down transistor being an NMOS type transistor and having its wall tied to its source; a second pull-up/pull-down transistor pair for connection between a second ground reference and a second Vcc supply, the second pull-up/pull-down transistor pair coupled for driving said output terminal, said second ground reference and said second Vcc supply are isolated from said first ground reference and said first Vcc supply within the integrated circuit and have separate corresponding pins on the integrated circuit for external connection, the second pull-down transistor being an NMOS type transistor having its well tied to its source wherein isolation is improved between said first ground reference, said first Vcc supply said second ground reference and said second Vcc supply; logic means for controlling the first pull-up/pull-down transistor pair such that initial switching of said output terminal is powered by said first ground reference and said first Vcc supply, and such that maintenance of said output terminal at a HIGH or LOW state is powered by said second ground reference and said second Vcc supply, wherein the switching of one buffer within the integrated circuit will not disturb the output state of another, quiescent buffer within the integrated circuit; and a pair of diodes one each connected in series between said output terminal and each of the pull-up transistor and the pull-down transistor in the first transistor pair.
Claim 5
Dependent Claim
270 words
A p-well process type integrated circuit having a plurality of buffers, each buffer comprising: a first pull-up/pull-down transistor pair for connection between a first ground reference and a first Vcc supply, the first pull-up/pull-down transistor pair coupled for driving an output terminal, the first pull-down transistor being an NMOS type transistor and having its wall tied to its source; a second pull-up/pull-down transistor pair for connection between a second ground reference and a second Vcc supply, the second pull-up/pull-down transistor pair coupled for driving said output terminal, said second ground reference and said second Vcc supply are isolated from said first ground reference and said first Vcc supply within the integrated circuit and have separate corresponding pins on the integrated circuit for external connection, the second pull-down transistor being an NMOS type transistor having its well tied to its source wherein isolation is improved between said first ground reference, said first Vcc supply said second ground reference and said second Vcc supply; logic means for controlling the first pull-up/pull-down transistor pair such that initial switching of said output terminal is powered by said first ground reference and said first Vcc supply, and such that maintenance of said output terminal at a HIGH or LOW state is powered by said second ground reference and said second Vcc supply, wherein the switching of one buffer within the integrated circuit will not disturb the output state of another, quiescent buffer within the integrated circuit; and a pair of diodes one each connected in series between said output terminal and each of the pull-up transistor and the pull-down transistor in the first transistor pair.
Claim 6
Dependent Claim
14 words
The integrated circuit of claim 3, wherein: the pair of diodes comprise Schottky diodes.
Claim 7
Dependent Claim
288 words
A p-well process type CMOS integrated circuit having a plurality of buffers, each buffer comprising: a first pull-up/pull-down transistor pair for connection between a first ground reference and a first Vcc supply, the first pull-up/pull-down transistor pair coupled for driving an output terminal, the first pull-down transistor being an NMOS type transistor and having its well tied to its source; a second pull-up/pull-down transistor pair for connection between a second ground reference and a second Vcc supply, the second pull-up/pull-down transistor pair coupled for driving said output terminal, said second ground reference and said second Vcc supply are isolated from said first ground reference and said first Vcc supply within the integrated circuit and have separate corresponding pins on the integrated circuit for external connection, the second pull-down transistor being an NMOS type transistor disposed in a p-well separate from a p-well in which the first pull-down transistor is disposed, and having its well tied to its source wherein isolation is improved between said first ground reference, said first Vcc supply, said second ground reference and said second Vcc supply; logic means for controlling the first pull-up/pull-down transistor pair such that initial switching of said output terminal is powered by said first ground reference and said first Vcc supply, and such that maintenance of said output terminal at a HIGH or LOW state is powered by said second ground reference and said second Vcc supply, wherein the switching of one buffer within the integrated circuit will not disturb the output state of another, quiescent buffer within the integrated circuit; and a pair of diodes one each connected in series between said output terminal and each of the pull-up transistor and the pull-down transistor in the first transistor pair.
Claim 8
Dependent Claim
288 words
A p-well process type CMOS integrated circuit having a plurality of buffers, each buffer comprising: a first pull-up/pull-down transistor pair for connection between a first ground reference and a first Vcc supply, the first pull-up/pull-down transistor pair coupled for driving an output terminal, the first pull-down transistor being an NMOS type transistor and having its well tied to its source; a second pull-up/pull-down transistor pair for connection between a second ground reference and a second Vcc supply, the second pull-up/pull-down transistor pair coupled for driving said output terminal, said second ground reference and said second Vcc supply are isolated from said first ground reference and said first Vcc supply within the integrated circuit and have separate corresponding pins on the integrated circuit for external connection, the second pull-down transistor being an NMOS type transistor disposed in a p-well separate from a p-well in which the first pull-down transistor is disposed, and having its well tied to its source wherein isolation is improved between said first ground reference, said first Vcc supply, said second ground reference and said second Vcc supply; logic means for controlling the first pull-up/pull-down transistor pair such that initial switching of said output terminal is powered by said first ground reference and said first Vcc supply, and such that maintenance of said output terminal at a HIGH or LOW state is powered by said second ground reference and said second Vcc supply, wherein the switching of one buffer within the integrated circuit will not disturb the output state of another, quiescent buffer within the integrated circuit; and a pair of diodes one each connected in series between said output terminal and each of the pull-up transistor and the pull-down transistor in the first transistor pair.
Claim 9
Dependent Claim
14 words
The integrated circuit of claim 5, wherein: the pair of diodes comprise Schottky diodes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-06 | 1997-12-06 | 1998-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-06 | 2001-12-06 | 2002-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-06 | 2005-12-06 | 2006-06-07 | $7700.00 | Window Closed / Lapsed |