Patent US5319232A successfully refreshed from Google Patents.
US5319232A
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US
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Transistor having a lightly doped region
Assignee: NXP USA Inc
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Filing: 1993-06-14
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Granted: 1994-06-07
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Expires: 2013-06-14
Abstract
Abstract A transistor (10 or 11) and method of formation. The transistor (10) has a substrate (12). The substrate (12) has an overlying dielectric layer (14) and an insulated conductive control electrode (16) which overlies the dielectric layer (14). A dielectric region (18) overlies the insulated conductive control electrode (16), and a dielectric region (20) is adjacent to the insulated conductive control electrode (16). A spacer (30) is adjacent to the dielectric region (20). Epitaxial regions (24) are adjacent to the spacer (30) and the spacer (30) is overlying portions of the epitaxial regions (24). A dielectric region (26) overlies the epitaxial regions (24). Highly doped source and drain regions (32) underlie the epitaxial regions (24). LDD regions (28), which are underlying the spacer (30), are adjacent to and electrically connected to the source and drain regions (32).
Inventors
- 👤 James R. Pfiester
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:58
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0275; H10D10/00; H10D10/01; H10D10/051; H10D10/054; H10D30/022; H10D64/00; H10D64/01; H10D64/015; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
312 words
A lightly doped drain transistor on a substrate material wherein the transistor has an insulated conductive gate having a first sidewall and a second sidewall, the lightly doped drain transistor comprising: a first elevated electrode region laterally separated from said insulated conductive gate, said first elevated electrode region having a sidewall facing the first sidewall of the insulated conductive gate, the first elevated electrode region being made of same material as the substrate material; a second elevated electrode region laterally separated from said insulated conductive gate, said second elevated electrode region having a sidewall facing the second sidewall of the insulated conductive gate, the second elevated electrode region being made of same material as the substrate material; a lightly doped source region and a lightly doped drain region adjacent the insulated conductive gate, the lightly doped source region having a doping depth and a first edge which is defined and limited by the sidewall of the first elevated electrode region and a second edge which is defined and limited by a sidewall of the insulated conductive gate, and the lightly doped drain region having a doping depth and having an edge which is defined and limited by the sidewall of the second elevated electrode region; and a heavily doped source region and a heavily doped drain region respectively adjacent the lightly doped source and drain regions, the heavily doped source region having a first interface with the substrate material and a second interface with the lightly doped source region and the heavily doped drain region having a first interface with the substrate material and a second interface with the lightly doped drain region, the heavily doped source and drain regions each having a doping depth, the respective doping depth of the lightly doped source and drain regions being greater than the respective doping depth of the heavily doped source and drain regions.
Claim 2
Dependent Claim
312 words
A lightly doped drain transistor on a substrate material wherein the transistor has an insulated conductive gate having a first sidewall and a second sidewall, the lightly doped drain transistor comprising: a first elevated electrode region laterally separated from said insulated conductive gate, said first elevated electrode region having a sidewall facing the first sidewall of the insulated conductive gate, the first elevated electrode region being made of same material as the substrate material; a second elevated electrode region laterally separated from said insulated conductive gate, said second elevated electrode region having a sidewall facing the second sidewall of the insulated conductive gate, the second elevated electrode region being made of same material as the substrate material; a lightly doped source region and a lightly doped drain region adjacent the insulated conductive gate, the lightly doped source region having a doping depth and a first edge which is defined and limited by the sidewall of the first elevated electrode region and a second edge which is defined and limited by a sidewall of the insulated conductive gate, and the lightly doped drain region having a doping depth and having an edge which is defined and limited by the sidewall of the second elevated electrode region; and a heavily doped source region and a heavily doped drain region respectively adjacent the lightly doped source and drain regions, the heavily doped source region having a first interface with the substrate material and a second interface with the lightly doped source region and the heavily doped drain region having a first interface with the substrate material and a second interface with the lightly doped drain region, the heavily doped source and drain regions each having a doping depth, the respective doping depth of the lightly doped source and drain regions being greater than the respective doping depth of the heavily doped source and drain regions.
Claim 3
Dependent Claim
286 words
A transistor comprising: a substrate material and a conductive control region overlying the substrate material, the conductive control region having a width; a dielectric region overlying the conductive control region; a spacer adjacent a perimeter of the conductive control region; doped epitaxial regions formed from same material as the substrate material and being adjacent to and partially underlying the spacer, each of the doped epitaxial regions being laterally separated from the conductive control region to form separation openings wherein each of the separation openings has a width and is filled by said spacer, each of the separation openings having a first sidewall defined by an epitaxial region and a second sidewall defined by the conductive control region; doped portions of the substrate material underlying the spacer forming a first doped region and a second doped region, the first and second doped regions each having a width defined and limited by the width of one of said separation openings, the first and second doped regions each having a doping depth; and a third doped region and a fourth doped region underlying the doped epitaxial regions, the third doped region being connected to the first doped region and the fourth doped region being connected to the second doped region, the third doped region having a first interface with the substrate material and a second interface with the first doped region, and the fourth doped region having a first interface with the substrate material and a second interface with the second doped region, the third and fourth doped regions each having a doping depth, the respective doping depth of the first and second doped regions being greater than the respective doping depth of the third and fourth doped regions.
Claim 4
Dependent Claim
286 words
A transistor comprising: a substrate material and a conductive control region overlying the substrate material, the conductive control region having a width; a dielectric region overlying the conductive control region; a spacer adjacent a perimeter of the conductive control region; doped epitaxial regions formed from same material as the substrate material and being adjacent to and partially underlying the spacer, each of the doped epitaxial regions being laterally separated from the conductive control region to form separation openings wherein each of the separation openings has a width and is filled by said spacer, each of the separation openings having a first sidewall defined by an epitaxial region and a second sidewall defined by the conductive control region; doped portions of the substrate material underlying the spacer forming a first doped region and a second doped region, the first and second doped regions each having a width defined and limited by the width of one of said separation openings, the first and second doped regions each having a doping depth; and a third doped region and a fourth doped region underlying the doped epitaxial regions, the third doped region being connected to the first doped region and the fourth doped region being connected to the second doped region, the third doped region having a first interface with the substrate material and a second interface with the first doped region, and the fourth doped region having a first interface with the substrate material and a second interface with the second doped region, the third and fourth doped regions each having a doping depth, the respective doping depth of the first and second doped regions being greater than the respective doping depth of the third and fourth doped regions.
Claim 5
Dependent Claim
74 words
The transistor of claim 2 wherein the third doped region is doped more than the first doped region, and the fourth doped region is doped more than the second doped region, the first doped region being electrically connected to the third doped region, the first and third doped regions forming a drain, and the second doped region being electrically connected to the fourth doped region, the second and fourth doped regions forming a source.
Claim 6
Dependent Claim
21 words
The transistor of claim 2 wherein the doped epitaxial region further comprises a dielectric layer formed overlying the doped epitaxial region.
Claim 7
Dependent Claim
55 words
The transistor of claim 2 wherein: the first, second, third, and fourth doped regions are each doped with a dopant of a first conductivity type, the first, second, third, and fourth doped regions acting as a portion of a base; and the conductive control region is doped with a dopant of a second conductivity type.
Claim 8
Dependent Claim
105 words
The transistor of claim 5 further comprising: a fifth doped region, doped with the dopant of the second conductivity type, underling and connecting to the conductive control region, the fifth doped region and the conductive control region acting as an emitter; a sixth doped region, doped with the dopant of the first conductivity type, surrounding the fifth doped region, the sixth doped region connecting to the first and second doped regions, the sixth doped region completing formation of the base; and a seventh doped region which surrounds the first, second, third, fourth, fifth, and sixth doped regions, the seventh doped region acting as a collector.
Claim 9
Dependent Claim
65 words
The transistor of claim 2 wherein the first, second, third, and fourth doped regions respectively have first, second, third, and fourth doping depths, the first and third doped regions being electrically connected, and the second and fourth doped regions being electrically connected, the first doping depth being greater than the third doping depth, and the second doping depth being greater than the fourth doping depth.
Claim 10
Dependent Claim
21 words
The transistor of claim 1 wherein the lightly doped drain region and the lightly doped source region are ion implanted regions.
Claim 11
Dependent Claim
21 words
The transistor of claim 1 wherein the heavily doped drain region and the heavily doped source region are ion implanted regions.
Claim 12
Dependent Claim
28 words
The transistor of claim 1 wherein the first and second elevated electrode regions are formed epitaxially as the same material which is used to form the substrate material.
Claim 13
Dependent Claim
37 words
The transistor of claim 1 wherein the lightly doped source region and the lightly doped drain region comprise: a doping-accessible portion of the substrate material formed by removing a spacer which is adjacent said insulated conductive gate.
Claim 14
Dependent Claim
181 words
A transistor on a substrate material wherein said transistor has a control electrode which overlies the substrate material, the transistor comprising: an elevated electrode region laterally separated from the control electrode to form a separation region, the elevated electrode region being made of same material as the substrate material; a lightly doped region adjacent the control electrode and within the substrate material, the lightly doped region having both a doping depth and a doping width, the doping width being defined and limited by the separation region; and a heavily doped region adjacent the lightly doped region, the heavily doped region having both a doping depth and a doping width, the doping width being measured in the same direction as the doping width of the lightly doped region, the doping depth of the lightly doped region being greater than the doping depth of the heavily doped region, the doping width of the lightly doped region being less than the doping width of the heavily doped region, the lightly doped region being positioned closer to the control electrode than the heavily doped region.
Claim 15
Dependent Claim
181 words
A transistor on a substrate material wherein said transistor has a control electrode which overlies the substrate material, the transistor comprising: an elevated electrode region laterally separated from the control electrode to form a separation region, the elevated electrode region being made of same material as the substrate material; a lightly doped region adjacent the control electrode and within the substrate material, the lightly doped region having both a doping depth and a doping width, the doping width being defined and limited by the separation region; and a heavily doped region adjacent the lightly doped region, the heavily doped region having both a doping depth and a doping width, the doping width being measured in the same direction as the doping width of the lightly doped region, the doping depth of the lightly doped region being greater than the doping depth of the heavily doped region, the doping width of the lightly doped region being less than the doping width of the heavily doped region, the lightly doped region being positioned closer to the control electrode than the heavily doped region.
Claim 16
Dependent Claim
28 words
The transistor of claim 12 wherein the lightly doped region and the heavily doped region form an electrode of the transistor wherein the transistor is a bipolar transistor.
Claim 17
Dependent Claim
31 words
The transistor of claim 12 wherein the heavily doped region and the lightly doped region are electrically coupled to form one of either a source or a drain of said transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-06 | 1997-12-06 | 1998-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-06 | 2001-12-06 | 2002-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-06 | 2005-12-06 | 2006-06-07 | $7700.00 | Window Closed / Lapsed |