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US5317215A
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Method and apparatus for frequency discriminating computer network signals
Assignee: HP Inc
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Filing: 1992-12-01
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Granted: 1994-05-31
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Expires: 2012-12-01
Abstract
Abstract A digital frequency discrimination circuit includes an edge detector coupled to receive a transmission signal for producing an edge detected signal; an edge timer including a shift register clocked by the clock signal and having the edge detected signal as a data input, and a timeout determining subcircuit having a plurality of bits of the shift register coupled as edge detection inputs, for determining and providing a timeout signal indicating whether any of the edge detection inputs represents an edge detection; and a state machine circuit coupled to receive the clock signal, the edge detected signal, and the timeout signal for producing an unsquelch signal indicating whether the transmission signal meets frequency discrimination requirements.
Inventors
- 👤 David A. Kranzler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 05:01
CPC Classifications
G; G01; G01R; G01R23/00; G01R23/02
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
189 words
In a receiver for a Local Area Network (LAN) environment, a frequency discrimination circuit accepting as input a clock signal and a transmission signal, the frequency discrimination circuit comprising: a) an edge detector coupled to receive the clock signal and the transmission signal as inputs for producing an edge detected signal; b) an edge timer coupled to receive the clock signal and the edge detected signal as inputs for producing a timeout signal; and c) a state machine circuit coupled to receive the clock signal, the edge detected signal, and the timeout signal for producing an unsquelch signal indicating whether the transmission signal meets frequency discrimination requirements; wherein the edge detected signal is synchronous with the clock signal; wherein the edge timer comprises a shift register clocked by the clock signal and having the edge detected signal as a data input; and wherein the edge timer further comprises a timeout determining means having edge detection inputs, with a plurality of bits of the shift register coupled as edge detection inputs, for determining and providing a timeout signal indicating that none of the edge detection inputs represents an edge detection.
Claim 2
Dependent Claim
189 words
In a receiver for a Local Area Network (LAN) environment, a frequency discrimination circuit accepting as input a clock signal and a transmission signal, the frequency discrimination circuit comprising: a) an edge detector coupled to receive the clock signal and the transmission signal as inputs for producing an edge detected signal; b) an edge timer coupled to receive the clock signal and the edge detected signal as inputs for producing a timeout signal; and c) a state machine circuit coupled to receive the clock signal, the edge detected signal, and the timeout signal for producing an unsquelch signal indicating whether the transmission signal meets frequency discrimination requirements; wherein the edge detected signal is synchronous with the clock signal; wherein the edge timer comprises a shift register clocked by the clock signal and having the edge detected signal as a data input; and wherein the edge timer further comprises a timeout determining means having edge detection inputs, with a plurality of bits of the shift register coupled as edge detection inputs, for determining and providing a timeout signal indicating that none of the edge detection inputs represents an edge detection.
Claim 3
Dependent Claim
53 words
The frequency discrimination circuit of claim 1, wherein the shift register has an additional bit, wherein the frequency discrimination circuit additionally comprises a timeout mode input, and means, under control of the timeout mode input, for selectably providing the additional shift register bit as an edge detection input to the timeout determining means.
Claim 4
Dependent Claim
77 words
The frequency discrimination circuit of claim 1, wherein the edge detector samples the transmission signal at both falling edges and rising edges of the clock signal, and wherein the edge timer comprises: i) a first shift register clocked by rising edges of the clock signal and having the edge detected signal as an input; and ii) a second shift register clocked by falling edges of the clock signal and having the edge detected signal as an input.
Claim 5
Dependent Claim
67 words
The frequency discrimination circuit of claim 3, wherein the first shift register has a first additional bit, wherein the second shift register has a second additional bit, wherein the frequency discrimination circuit additionally comprises a timeout mode input, and means, under control of the timeout mode input, for selectably providing the first and second additional shift register bits as edge detection inputs to the timeout determining means.
Claim 6
Dependent Claim
140 words
In a receiver for receiving a network transmission signal of a local area network, a frequency discrimination circuit comprising: a) an edge detector coupled to receive the network transmission signal as an input, for producing an edge detected signal; b) an edge timer comprising i) a shift register clocked by a clock signal and having the edge detected signal as a data input, and ii) a timeout determining means having edge detection inputs, with a plurality of bits of the shift register coupled as edge detection inputs, for determining and providing a timeout signal indicating that none of the edge detection inputs represents an edge detection; and c) a state machine circuit coupled to receive the clock signal, the edge detected signal, and the timeout signal for producing an unsquelch signal indicating whether the transmission signal meets frequency discrimination requirements.
Claim 7
Dependent Claim
140 words
In a receiver for receiving a network transmission signal of a local area network, a frequency discrimination circuit comprising: a) an edge detector coupled to receive the network transmission signal as an input, for producing an edge detected signal; b) an edge timer comprising i) a shift register clocked by a clock signal and having the edge detected signal as a data input, and ii) a timeout determining means having edge detection inputs, with a plurality of bits of the shift register coupled as edge detection inputs, for determining and providing a timeout signal indicating that none of the edge detection inputs represents an edge detection; and c) a state machine circuit coupled to receive the clock signal, the edge detected signal, and the timeout signal for producing an unsquelch signal indicating whether the transmission signal meets frequency discrimination requirements.
Claim 8
Dependent Claim
30 words
The frequency discrimination circuit of claim 5, wherein the state machine circuit is further for producing a LinkPulse signal indicating whether the transmission signal meets requirements for a valid LinkPulse.
Claim 9
Dependent Claim
62 words
The frequency discrimination circuit of claim 6, wherein the transmission signal is transmitted in twisted pair format having an RD+ line and an RD- line, and wherein the state machine circuit additionally receives the transmission signal and is further for producing a polarity signal indicating a polarity of the RD+ line with respect to the RD- line during and end of packet.
Claim 10
Dependent Claim
38 words
The frequency discrimination circuit of claim 7, wherein the state machine circuit receives the transmission signal in TTL format and comprises means for sampling the transmission signal under control of the timeout signal to produce the polarity signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-30 | 1997-11-29 | 1998-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-30 | 2001-11-29 | 2002-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-30 | 2005-11-29 | 2006-05-31 | $7700.00 | Window Closed / Lapsed |