Apparatus for detecting and recovering binary data from an input signal

Claim 2

Apparatus for recovering binary data from an input signal wherein each bit of said data has a predetermined time interval and wherein first and second voltage levels represent a 1 and 0 of said data respectively comprising: first means for deriving a synchronized clock from said data synchronized with respect to said predetermined time intervals including a first edge detector, a first counter and a second counter, said first edge detector having an input adapted for coupling to said input signal, said first edge detector including means for detecting transitions between said first and second voltage levels and for generating an output signal in response to said detected transitions, said first counter having a clock input, a reset input, and an output, said first counter resetting itself after counting up to a first predetermined value, said output signal of said first edge detector coupled to said reset input of said first counter for resetting said first counter at times a transition is detected, said second counter having a clock input, a reset input, and an output, said second counter resetting itself after counting up to a second predetermined value, said output of said first counter coupled to said reset input of said second counter for resetting said second counter at times said first counter reaches a third predetermined value, each said clock input of said first and second counters being responsive to a respective clock signal of a predetermined frequency, said output of said second counter providing said synchronized clock, second means having a first input coupled to said input signal and having a second input coupled to said synchronized clock at said output of said second counter for generating binary data from said input signal at an output, third means coupled to said first and second means for inhibiting said output of said second means as a function of the output of said first and second counters indicative of a nonsynchronized clock.

Claim 3

The apparatus of claim 1 wherein said first, second, and third predetermined values are equal.

Claim 4

The apparatus of claim 1 wherein said second means includes a one bit delay line having an input coupled to said input signal and an output coupled to an AND gate having a second input coupled to said input signal and wherein the output of said second counter is coupled to a clock input of said delay line.

Claim 5

The apparatus of claim 1 wherein said third means for inhibiting includes generating an inhibit signal at times the ratio of the frequency of the output of said first counter to the frequency of the output of said second counter is below a predetermined constant.

Claim 6

The apparatus of claim 1 further including means for providing a noise signal having first and second voltage levels with transitions therebetween corresponding to hard limited noise coupled to said input of said first edge detector at times said input signal is nonexistent.

Claim 7

The apparatus of claim 1 further including a second edge detector coupled between said output of said first counter and said reset input of said second counter.

Claim 8

The apparatus of claim 6 wherein said second edge detector includes means for detecting rising edge transitions only.

Claim 9

The apparatus of claim 1 wherein said third means includes an up/down counter having an up input coupled the output of said first counter and a down input coupled to the output of a divider, said divider having a numerator input coupled to the output of said second counter.

Claim 10

The apparatus of claim 8 wherein said third means further includes a comparator having an input coupled to the output of said up/down counter and having an output coupled to said second means.

Claim 11

Apparatus for recovering binary data from a phase coded radio frequency signal wherein each bit of said data has a predetermined time interval and for inhibiting an output data signal at times said phase coded radio frequency signal is absent comprising: a radio receiver including a mixer, an intermediate frequency amplifier having a predetermined bandwidth, a hard limiter and a phase detector coupled in series for providing first and second voltage levels corresponding to the phase of said data during said predetermined time intervals at times said phase coded radio frequency signal is received and for providing first and second voltage levels with transitions therebetween corresponding to hard limited noise at a frequency above the frequency of transitions between said first and second voltage levels arising from said binary data, first means for deriving a synchronized clock from said data synchronized with respect to said predetermined time intervals including a first edge detector, a first counter and a second counter, said first edge detector coupled to the output of said phase detector for detecting transitions between said first and second voltage levels and for generating an output signal in response to said detected transitions, said first counter having a clock input, a reset input, and an output, said first counter resetting itself after counting up to a first predetermined value, said output signal of said first edge detector coupled to said reset input of said first counter for resetting said first counter at times a transition is detected, said second counter having a clock input, a reset input, and an output, said second counter resetting itself after counting up to a second predetermined value, said output of said first counter coupled to said reset input of said second counter for resetting said second counter at times said first counter reaches a third predetermined value, each said clock input of said first and second counters being responsive to a respective clock signal of a predetermined frequency, said output of said second counter providing said synchronized clock, second means having a first input coupled to said input signal and having a second input coupled to said synchronized clock at said output of said second counter for generating binary data from said input signal at an output, third means coupled to said first and second means for inhibiting said output of said second means as a function of the output of said first and second counters indicative of a nonsynchronized clock.

Claim 12

Apparatus for recovering binary data from a phase coded radio frequency signal wherein each bit of said data has a predetermined time interval and for inhibiting an output data signal at times said phase coded radio frequency signal is absent comprising: a radio receiver including a mixer, an intermediate frequency amplifier having a predetermined bandwidth, a hard limiter and a phase detector coupled in series for providing first and second voltage levels corresponding to the phase of said data during said predetermined time intervals at times said phase coded radio frequency signal is received and for providing first and second voltage levels with transitions therebetween corresponding to hard limited noise at a frequency above the frequency of transitions between said first and second voltage levels arising from said binary data, first means for deriving a synchronized clock from said data synchronized with respect to said predetermined time intervals including a first edge detector, a first counter and a second counter, said first edge detector coupled to the output of said phase detector for detecting transitions between said first and second voltage levels and for generating an output signal in response to said detected transitions, said first counter having a clock input, a reset input, and an output, said first counter resetting itself after counting up to a first predetermined value, said output signal of said first edge detector coupled to said reset input of said first counter for resetting said first counter at times a transition is detected, said second counter having a clock input, a reset input, and an output, said second counter resetting itself after counting up to a second predetermined value, said output of said first counter coupled to said reset input of said second counter for resetting said second counter at times said first counter reaches a third predetermined value, each said clock input of said first and second counters being responsive to a respective clock signal of a predetermined frequency, said output of said second counter providing said synchronized clock, second means having a first input coupled to said input signal and having a second input coupled to said synchronized clock at said output of said second counter for generating binary data from said input signal at an output, third means coupled to said first and second means for inhibiting said output of said second means as a function of the output of said first and second counters indicative of a nonsynchronized clock.

Claim 13

The apparatus of claim 10 wherein said first, second, and third predetermined values are equal.

Claim 14

The apparatus of claim 10 wherein said second means includes a one bit delay line having an input coupled to said input signal and an output coupled to an AND gate having a second input coupled to said input signal and wherein the output of said second counter is coupled to a clock input of said delay line.

Claim 15

The apparatus of claim 10 wherein said third means for inhibiting includes generating an inhibit signal at times the ratio of the frequency of the output of said first counter to the frequency of the output of said second counter is below a predetermined constant.

Claim 18

Apparatus for deriving a synchronized clock from an input signal containing binary data wherein each bit of said data has a predetermined time interval and wherein first and second voltage levels represent a 1 or 0 of said data respectively comprising: a first edge detector having an input adapted for coupling to said input signal, said first edge detector including means for detecting transitions between said first and second voltage levels and for generating an output signal in response to said detected transitions, a first counter having a clock input, a reset input, and an output, said first counter resetting itself after counting up to a first predetermined value, said output signal of said first edge detector coupled to said reset input of said first counter for resetting said first counter at times a transition is detected, and a second counter having a clock input, a reset input, and an output, said second counter resetting itself after counting up to a second predetermined value, said output of said first counter coupled to said reset input of said second counter for resetting said second counter at times said first counter reaches a third predetermined value, each said clock input of said first and second counters being responsive to a respective clock signal of a predetermined frequency, said output of said second counter providing said synchronized clock.

Claim 19

Apparatus for deriving a synchronized clock from an input signal containing binary data wherein each bit of said data has a predetermined time interval and wherein first and second voltage levels represent a 1 or 0 of said data respectively comprising: a first edge detector having an input adapted for coupling to said input signal, said first edge detector including means for detecting transitions between said first and second voltage levels and for generating an output signal in response to said detected transitions, a first counter having a clock input, a reset input, and an output, said first counter resetting itself after counting up to a first predetermined value, said output signal of said first edge detector coupled to said reset input of said first counter for resetting said first counter at times a transition is detected, and a second counter having a clock input, a reset input, and an output, said second counter resetting itself after counting up to a second predetermined value, said output of said first counter coupled to said reset input of said second counter for resetting said second counter at times said first counter reaches a third predetermined value, each said clock input of said first and second counters being responsive to a respective clock signal of a predetermined frequency, said output of said second counter providing said synchronized clock.

Claim 20

The apparatus of claim 15 wherein said first, second, and third predetermined values are equal.

Claim 21

The apparatus of claim 15 further including means for providing a noise signal having first and second voltage levels with transitions therebetween corresponding to hard limited noise coupled to said input of said first edge detector at times said input signal is nonexistent.

Claim 22

The apparatus of claim 15 further including a second edge detector coupled between said output of said first counter and said reset input of said second counter.

Claim 23

The apparatus of claim 18 wherein said second edge detector includes means for detecting rising edge transitions only.