Patent US2319898A successfully refreshed from Google Patents.
US3789303A
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Method and apparatus for synchronizing split-phase pcm signals
Assignee: United States Department of the Navy
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Filing: 1972-05-01
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Granted: 1974-01-29
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Expires: 1992-05-01
Abstract
Abstract This is a device for resolving ambiguity of the start of a split-phase coded data bit. The device is initially synchronized with the zero crossings or polarity transition points in the coded data. A first integrator integrates the signal over onehalf the data bit interval, and holds this value. A second integrator integrates the signal over the successive portion of the data bit interval and these two integrator signals are then compared. When the receiver clock is initially synchronized with a data bit polarity reversal, but not at the start of the data bit interval, the integrated signals will be of the same polarity and the comparator will so indicate this fact. To bring the receiver clock into synchronization with the start of the data bit interval, it is necessary to shift the clock output in time to be synchronized with the next successive polarity reversal or zero crossing. This is accomplished by a counting technique which resolves ambiguity introduced by attendant noise in the data transmission. A counter receives a predetermined number of minimum error signals within a given period of time. These error signals are signals out of the comparator indicating the same polarities for the integrated signals. As noise will sometimes cause this result when the clock is initially properly synchronized, reliability is increased by holding the initial synchronization until a minimum number of error signals are received, indicating the clock is not synchronized.
Inventors
- 👤 E Hoffman
- 👤 J Loessi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:11
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0332; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
248 words
A system for synchronizing a clock with the start of each bit of a split-phase data bit stream, comprising: a first clock; a pair of integrators, one integrator receiving one time interval of continuous polarity within a split-phase data bit period and producing a signal indicative of that polarity, and another integrator receiving a consecutive time interval of continuous opposite polarity within a split phase data bit period and producing a signal indicative of that opposite polarity; a comparator connected to the output of said pair of integrators for comparing the polarity of the signals and producing an error signal when the polarities are the same; a first counter connected to the output of said comparator to count the error signals; a phase shifter connected to the output of said first counter and to the input of said first clock far synchronizing said first clock with the start of each split phase data bit in response to a first predetermined number of error signals; a second clock connected to and having twice the frequency of said first clock to effect the synchronization thereof, said second clock being initially synchronized with the zero crossings of the split phase data bits in the absence of error signals from said comparator; and a second counter connected between said second clock and said first counter, responsive to said second clock for cyclically counting a second predetermined number of clock pulses and resetting said first counter to zero when the number is attained.
Claim 2
Independent Claim
248 words
A system for synchronizing a clock with the start of each bit of a split-phase data bit stream, comprising: a first clock; a pair of integrators, one integrator receiving one time interval of continuous polarity within a split-phase data bit period and producing a signal indicative of that polarity, and another integrator receiving a consecutive time interval of continuous opposite polarity within a split phase data bit period and producing a signal indicative of that opposite polarity; a comparator connected to the output of said pair of integrators for comparing the polarity of the signals and producing an error signal when the polarities are the same; a first counter connected to the output of said comparator to count the error signals; a phase shifter connected to the output of said first counter and to the input of said first clock far synchronizing said first clock with the start of each split phase data bit in response to a first predetermined number of error signals; a second clock connected to and having twice the frequency of said first clock to effect the synchronization thereof, said second clock being initially synchronized with the zero crossings of the split phase data bits in the absence of error signals from said comparator; and a second counter connected between said second clock and said first counter, responsive to said second clock for cyclically counting a second predetermined number of clock pulses and resetting said first counter to zero when the number is attained.
Claim 3
Dependent Claim
55 words
The synchronization system of claim 1 further including: integrate command means connected to said pair of integrators responsive to said first clock for triggering said first integrator to integrate each bit over said one interval of continuous polarity and for triggering said second integrator to integrate each bit over said consecutive interval of continuous polarity.
Claim 4
Independent Claim
156 words
A method for synchronizing a clock with the start of each split phase data bit interval in a data stream, comprising the steps of: comprising cyclically the polarities of the data signal within a data bit interval; producing an error signal when the signals are of the same polarity; counting the number of error signals produced by said comparison; phase shifting a first clock, initially synchronized with a data bit zero crossing to be in synchronization with the start of each data bit interval in response to a predetermined number of comparisons within a predetermined time; synchronizing intitially a second clock with a zero crossing in the data stream; triggering said first clock with a pulse from said second clock to run at one-half the rate of said second clock; and integrating the data signals to produce polarity indicative signals corresponding to an interval within each data bit when said bit is of the same polarity.
Claim 5
Independent Claim
156 words
A method for synchronizing a clock with the start of each split phase data bit interval in a data stream, comprising the steps of: comprising cyclically the polarities of the data signal within a data bit interval; producing an error signal when the signals are of the same polarity; counting the number of error signals produced by said comparison; phase shifting a first clock, initially synchronized with a data bit zero crossing to be in synchronization with the start of each data bit interval in response to a predetermined number of comparisons within a predetermined time; synchronizing intitially a second clock with a zero crossing in the data stream; triggering said first clock with a pulse from said second clock to run at one-half the rate of said second clock; and integrating the data signals to produce polarity indicative signals corresponding to an interval within each data bit when said bit is of the same polarity.
Claim 6
Dependent Claim
65 words
The method of claim 3 wherein said step of phase shifting said first clock further includes the steps of: holding said first clock at its initial synchronization in absence of said comparison in excess of a predetermined number within a predetermined time; and moving the first clock pulse output an interval equal to one-half the time segment of continuous polarity within a single data bit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-28 | 1977-07-30 | 1978-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-28 | 1981-07-30 | 1982-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-28 | 1985-07-30 | 1986-01-29 | $7700.00 | Window Closed / Lapsed |