Dual mode phase-locked loop

Claim 1

A phase-locked loop for generating an output signal having a selectable frequency, comprising: reference means for generating a reference signal: phase comparator means responsive to said output signal and said reference signal for generating a lead signal and a lag signal; a lowpass filter including a lag circuit for providing a relatively low cutoff frequency and a lead circuit for providing a relatively high cutoff frequency; a voltage-controlled oscillator coupled to the output of said lowpass filter, the output of said voltage-controlled oscillator providing said phase-locked loop output signal; transient means for comparing a phase error detected by said phase comparator to a predetermined phase error; and driver means coupled to said phase comparator means, said transient means, and said lowpass filter for charging said lag circuit in response to said lag signal and for discharging said lag circuit in response to said lead signal, and if a transient condition is sensed by said transient means then for charging said lead circuit in response to said lead signal and for discharging said lead circuit in response to said lag signal.