US5315552A
Expired / Lapsed
US
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Memory module, method for control thereof and method for setting fault bit table for use therewith
Assignee: Kawasaki Microelectronics Inc
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Filing: 1992-08-25
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Granted: 1994-05-24
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Expires: 2012-08-25
Abstract
Abstract A memory module implementing a desired memory capacity by use of a plurality of memory chips. The memory module has a fault bit substituting device that compensates for fault bits detected in any of the memory chips. This improves the yield of the memory module and lowers the production costs thereof without recourse to expensive equipment such as wafer processors.
Inventors
- 👤 Hideki Yoneda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:06
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76; G11C5/00; G11C5/02; G11C5/04; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
135 words
A memory module providing a required memory capacity using a plurality of memory chips, said memory module having fault bit substituting means for detecting access to a fault bit and selecting a substitute bit to replace the fault bit, wherein said fault bit substituting means comprises: a fault address coincidence circuit for detecting access to the fault bit using a fault bit table; a fault bit substitute memory; and a selection control circuit for selecting, if said fault address coincidence circuit detects access to the fault bit, a substitute address within said fault bit substitute memory without asserting a selection signal to said plurality of memory chips, the selection control circuit asserting said selection signal to said plurality of memory chips if said fault address coincidence circuit fails to detect access to the fault bit.
Claim 2
Dependent Claim
135 words
A memory module providing a required memory capacity using a plurality of memory chips, said memory module having fault bit substituting means for detecting access to a fault bit and selecting a substitute bit to replace the fault bit, wherein said fault bit substituting means comprises: a fault address coincidence circuit for detecting access to the fault bit using a fault bit table; a fault bit substitute memory; and a selection control circuit for selecting, if said fault address coincidence circuit detects access to the fault bit, a substitute address within said fault bit substitute memory without asserting a selection signal to said plurality of memory chips, the selection control circuit asserting said selection signal to said plurality of memory chips if said fault address coincidence circuit fails to detect access to the fault bit.
Claim 3
Dependent Claim
58 words
The memory module of claim 1, wherein said memory module is accessed in units of words, each word containing a predetermined number of bits, and wherein said fault bit substituting means detects access to an address associated with the fault bit and selects a substitute word to replace a word containing said fault bit with the substitute word.
Claim 4
Dependent Claim
48 words
The memory module of claim 1, wherein said fault bit table is a programmable logic array, the fault bit table selecting any one of a plurality of words in said fault bit substitute memory when a fault address of one of the plurality of memory chips is input.
Claim 5
Dependent Claim
19 words
The memory module of claim 1, wherein said fault bit table stores table data in a field programmable memory.
Claim 6
Dependent Claim
19 words
The memory module of claim 1, wherein said fault bit table stores table data in a random access memory.
Claim 7
Dependent Claim
80 words
A method for setting the fault bit table in the memory module of claim 1, said fault bit table having table data written into the fault bit table, said method comprising the steps of: retaining information about a location of the fault bit in each of the plurality of memory chips during testing of said memory chips; and writing said table data into said memory module by using the fault bit location in each memory chip of said memory module.
Claim 8
Dependent Claim
65 words
A method for setting the fault bit table in the memory module of claim 1, said fault bit table having table data written into the fault bit table, said method comprising the step of: writing said table data into said memory module by using a location of the fault bit of each of the plurality of memory chips discovered during testing of said memory module.
Claim 9
Dependent Claim
66 words
A method for setting the fault bit table in the memory module of claim 1, wherein said memory module is used in a computer system, said method comprising the step of: rewriting said fault bit table by using a location of the fault bit of each of the plurality of memory chips, if any fault bit is detected through a memory diagnosis by said computer system.
Claim 10
Independent Claim
93 words
A method for control of a memory module providing a required memory capacity using a plurality of memory chips, said method comprising the steps of: detecting access to a fault bit using a fault bit table; and selecting a substitute bit for replacing said fault bit, wherein said selecting step selects, if access to the fault bit is detected, a substitute address without asserting a selection signal to said plurality of memory chips, and asserts said selection signal to said plurality of memory chips if no access to the fault bit is detected.
Claim 11
Independent Claim
93 words
A method for control of a memory module providing a required memory capacity using a plurality of memory chips, said method comprising the steps of: detecting access to a fault bit using a fault bit table; and selecting a substitute bit for replacing said fault bit, wherein said selecting step selects, if access to the fault bit is detected, a substitute address without asserting a selection signal to said plurality of memory chips, and asserts said selection signal to said plurality of memory chips if no access to the fault bit is detected.
References Cited (Backward Citations)
US4426688A
Cited
US4450559A
Cited
US4453248A
Cited
US4483001A
Cited
US4488298A
Cited
JPS61180350A
Cited
JPH03191450A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-23 | 1997-11-22 | 1998-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-23 | 2001-11-22 | 2002-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-23 | 2005-11-22 | 2006-05-24 | $7700.00 | Window Closed / Lapsed |