Patent US5315174A successfully refreshed from Google Patents.
US5315174A
Expired / Lapsed
US
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Programmable output slew rate control
Assignee: Lattice Semiconductor Corp
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Filing: 1992-08-13
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Granted: 1994-05-24
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Expires: 2012-08-13
Abstract
Abstract An output buffer circuit is disclosed that minimizes ground bounce problems. The buffer circuit provides for an output pull-down pre-driver circuit that can be controlled by a programmable signal to minimize the ground bounce. By placing a strong and weak transistor on the gate of the output driver transistor and providing control circuitry for disabling the stronger transistor appropriately, an output signal is provided that can be driven quickly or slowly to its active level. By disabling the stronger transistor, ground bounce problems associated with high to low transitions of output drive transistor are significantly reduced.
Inventors
- 👤 Herman M. Chang
- 👤 Melvin Chan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:16
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018585; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
145 words
An output buffer circuit for receiving an input signal and providing an output signal, the output buffer circuit for reducing ground bounce of the output signal, the output buffer circuit including an output drive transistor, the driver transistor including a gate; the output buffer circuit comprising: a first active device coupled to the gate of the output driver transistor for charging the driver transistor at a first rate responsive to the input signal being at a first logical level; a second active device coupled to the gate of the output driver transistor for charging the driver transistor at a second rate responsive to the input signal being at a first logical level; the first active device being stronger than the second active device; and means for disabling the first active device responsive to a logic signal being provided thereto, whereby the ground bounce is minimized.
Claim 2
Dependent Claim
145 words
An output buffer circuit for receiving an input signal and providing an output signal, the output buffer circuit for reducing ground bounce of the output signal, the output buffer circuit including an output drive transistor, the driver transistor including a gate; the output buffer circuit comprising: a first active device coupled to the gate of the output driver transistor for charging the driver transistor at a first rate responsive to the input signal being at a first logical level; a second active device coupled to the gate of the output driver transistor for charging the driver transistor at a second rate responsive to the input signal being at a first logical level; the first active device being stronger than the second active device; and means for disabling the first active device responsive to a logic signal being provided thereto, whereby the ground bounce is minimized.
Claim 3
Dependent Claim
18 words
The output buffer circuit of claim 1 in which the logic signal is provided by a programmable unit.
Claim 4
Dependent Claim
19 words
The output buffer circuit of claim 1 in which the logic signal can be controlled by a programmable cell.
Claim 5
Dependent Claim
23 words
The output buffer circuit of claim 1 in which the logic signal provides an indication that the circuit is in an Edit mode.
Claim 6
Dependent Claim
18 words
The output buffer circuit of claim 1 in which the first active device comprises a first P-type transistor.
Claim 7
Dependent Claim
18 words
The output buffer circuit of claim 2 in which the second active device comprises a second P-type transistor.
Claim 8
Dependent Claim
42 words
The output buffer circuit of claim 3 in which the disabling means comprises: means for receiving a programmable signal; means for sensing the programmable signal coupled to the receiving means; and means for providing a disable signal responsive to the sensing means.
Claim 9
Dependent Claim
181 words
An output pull-down pre-driver circuit for receiving an input signal and providing an output signal, the pre-driver circuit for reducing ground bounce at the output signal, the pre-driver circuit being coupled to an output driver transistor, the driver transistor including a gate, the pre-driver circuit comprising: a first P-type transistor coupled to the gate of the output driver transistor for charging the driver transistor at a first rate responsive to the input signal being at a first logical level; a second P-type transistor coupled to the gate of the output driver transistor for charging the driver transistor at a second rate responsive to the input signal being at a first logical level; the first P-type transistor being stronger than the second P-type transistor; and means for disabling the first P-type transistor responsive to a logic signal being provided thereto, the disabling means further comprising; means for receiving the logic signal; means for sensing the logic signal coupled to the receiving means; and means for providing a disable signal to the first P-type transistor responsive to the sensing of the logic signal.
Claim 10
Dependent Claim
181 words
An output pull-down pre-driver circuit for receiving an input signal and providing an output signal, the pre-driver circuit for reducing ground bounce at the output signal, the pre-driver circuit being coupled to an output driver transistor, the driver transistor including a gate, the pre-driver circuit comprising: a first P-type transistor coupled to the gate of the output driver transistor for charging the driver transistor at a first rate responsive to the input signal being at a first logical level; a second P-type transistor coupled to the gate of the output driver transistor for charging the driver transistor at a second rate responsive to the input signal being at a first logical level; the first P-type transistor being stronger than the second P-type transistor; and means for disabling the first P-type transistor responsive to a logic signal being provided thereto, the disabling means further comprising; means for receiving the logic signal; means for sensing the logic signal coupled to the receiving means; and means for providing a disable signal to the first P-type transistor responsive to the sensing of the logic signal.
Claim 11
Dependent Claim
26 words
The pre-driver circuit of claim 8 in which the sensing means includes means to sense a plurality of logic signals to disable the first P-type transistor.
Claim 12
Dependent Claim
23 words
The pre-driver circuit of claim 8 in which one of the signals that will disable the first P-type transistor is an Edit signal.
Claim 13
Dependent Claim
17 words
The pre-driver circuit of claim 9 in which a logic signal is provided by a programmable cell.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-23 | 1997-11-22 | 1998-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-23 | 2001-11-22 | 2002-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-23 | 2005-11-22 | 2006-05-24 | $7700.00 | Window Closed / Lapsed |