US5070256A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bus transmitter having controlled trapezoidal slew rate
Assignee: Hewlett Packard Development Co LP
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Filing: 1989-09-01
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Granted: 1991-12-03
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Expires: 2009-09-01
Abstract
Abstract A transmitter circuit for transmitting a digital data signal over a bus in a digital data processing system includes a MOSFET bus driver transistor having a gate to drain capacitance C GD which substantially dominates other capacitances at the gate terminal. The bus driver transistor is driven by a buffer circuit having pull-up and pull-down transistors current through which is controlled by current sources. The gate terminal of the driver transistor is connected to, and controlled by, the node between the pull-up and pull-down transistors. The drain terminal of the driver transistor is connected to, and controls, a bus line. To assert a signal on the bus line, the pull-up transistor is turned on to drive current into the node at a rate governed by the current source, which increases the voltage level of the node. When the voltage level of the node reaches the driver transistor's threshold level, the driver transistor begins to turn on, allowing the voltage level of the bus line to drop. Contemporaneously, current flows into the node from the bus line through the driver transistor's high gate to drain capacitance, thereby limiting the voltage level of the node, and thus the current flow through the driver transistor. Thus, current flows through the driver transistor from the bus line in a manner controlled, in part, by the voltage level on the bus line. In negating a signal on the bus line, the operations are similar, with current flowing out of the node through the pull-down transistor and the driver transistor's gate to drain capacitance.
Inventors
- 👤 David S. Grondalski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:03
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948; H03K17/00; H03K17/16; H03K17/161; H03K17/162; H03K17/163; H03K19/003; H03K19/00346; H03K19/00361; H03K4/00; H03K4/94
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
250 words
A bus transmitter circuit comprising: A. a driver including a MOSFET driver transistor having a drain terminal for connection to a bus line, a gate terminal connected to a control node and a source terminal for connection to a source power supply, said MOSFET driver transistor having a relatively high inherent capacitance between its drain terminal and its gate terminal which substantially dominates other capacitances at said gate terminal to thereby provide an internal feedback path between said drain terminal and said control node; and B. a control buffer including a switched pull-up comprising a pull-up transistor and a pull-up current source, and a switched pull-down comprising a pull-down transistor and a pull-down current source, said pull-up transistor and said pull-down transistor being connected to said control node, said switched pull-up transistor and said switched pull-down transistor being further connected to receive a data input signal to control the control node of said driver in response to the condition of said data input signal, current through said pull-up transistor and said pull-down transistor to said control node being controlled by the respective current source to turn said driver on and off in a controlled manner, said internal feedback path providing a bidirectional path through said inherent capacitance for current flow between said control node and said bus to selectively control the voltage level of a signal at said control node and thereby control the rate at which said driver turns on and off in response to said data input signal.
Claim 2
Dependent Claim
250 words
A bus transmitter circuit comprising: A. a driver including a MOSFET driver transistor having a drain terminal for connection to a bus line, a gate terminal connected to a control node and a source terminal for connection to a source power supply, said MOSFET driver transistor having a relatively high inherent capacitance between its drain terminal and its gate terminal which substantially dominates other capacitances at said gate terminal to thereby provide an internal feedback path between said drain terminal and said control node; and B. a control buffer including a switched pull-up comprising a pull-up transistor and a pull-up current source, and a switched pull-down comprising a pull-down transistor and a pull-down current source, said pull-up transistor and said pull-down transistor being connected to said control node, said switched pull-up transistor and said switched pull-down transistor being further connected to receive a data input signal to control the control node of said driver in response to the condition of said data input signal, current through said pull-up transistor and said pull-down transistor to said control node being controlled by the respective current source to turn said driver on and off in a controlled manner, said internal feedback path providing a bidirectional path through said inherent capacitance for current flow between said control node and said bus to selectively control the voltage level of a signal at said control node and thereby control the rate at which said driver turns on and off in response to said data input signal.
Claim 3
Dependent Claim
59 words
A bus transmitter circuit as defined in claim 1 further comprising a driver pull-down transistor connected to the control node and controlled by a pull-down control signal complementary to the data input signal to condition the control node to a selected level when the data input signal shifts levels to thereby facilitate a rapid turn-off of the driver transistor.
Claim 4
Dependent Claim
22 words
A bus transmitter circuit as defined in claim 1 wherein said pull-up transistor and said pull-down transistor are of different conductivity types.
Claim 5
Dependent Claim
33 words
A bus transmitter circuit as defined in claim 2 further comprising an inverter for receiving said pull-down control signal and producing said data input signal as the complement of said pull-down control signal.
Claim 6
Dependent Claim
366 words
A bus transmitter circuit comprising: A. a driver including a MOSFET driver transistor having a drain terminal for connection to a bus line, a gate terminal connected to a control node and a source terminal for connection to a source power supply, said MOSFET driver transistor having a relatively high inherent capacitance between its drain terminal and its gate terminal which substantially dominates other capacitances at said gate terminal to thereby provide an internal feedback path between said drain terminal and said control node; B. a control buffer including: i. a switched pull-up comprising: a. a pull-up current source for supplying current at a controlled rate; b. a pull-up transistor of a selected conductivity type having a drain terminal connected to said pull-up current source, a source terminal connected to said control node, and a gate terminal; ii. a switched pull-down comprising: a. a pull-down current source for supplying current at a controlled rate; b. a pull-down transistor of a different conductivity type than said pull-up transistor, said pull-down transistor having a drain terminal connected to said control node, a source terminal connected to said pull-down current source, and a gate terminal; the gate terminals of both said pull-up transistor and said pull-down transistor being connected to receive said data input signal, current through said pull-up transistor to said control node being controlled by said pull-up current source and through said pull-down transistor to said control node being controlled by the pull-down current source to turn said driver on and off in a controlled manner, said feedback path providing a bidirectional path through said inherent capacitance for current flow between said control node and said bus to selectively control the voltage level of a signal at said control node and thereby control the rate at which said driver turns on and off in response to said data input signal; and c. a driver pull-down transistor having a drain terminal connected to the control node and a gate terminal controlled by a pull-down control signal complementary to said data input signal to condition the control node to a selected level when the data input signal shifts levels to thereby facilitate a rapid turn-off of the driver transistor.
Claim 7
Dependent Claim
366 words
A bus transmitter circuit comprising: A. a driver including a MOSFET driver transistor having a drain terminal for connection to a bus line, a gate terminal connected to a control node and a source terminal for connection to a source power supply, said MOSFET driver transistor having a relatively high inherent capacitance between its drain terminal and its gate terminal which substantially dominates other capacitances at said gate terminal to thereby provide an internal feedback path between said drain terminal and said control node; B. a control buffer including: i. a switched pull-up comprising: a. a pull-up current source for supplying current at a controlled rate; b. a pull-up transistor of a selected conductivity type having a drain terminal connected to said pull-up current source, a source terminal connected to said control node, and a gate terminal; ii. a switched pull-down comprising: a. a pull-down current source for supplying current at a controlled rate; b. a pull-down transistor of a different conductivity type than said pull-up transistor, said pull-down transistor having a drain terminal connected to said control node, a source terminal connected to said pull-down current source, and a gate terminal; the gate terminals of both said pull-up transistor and said pull-down transistor being connected to receive said data input signal, current through said pull-up transistor to said control node being controlled by said pull-up current source and through said pull-down transistor to said control node being controlled by the pull-down current source to turn said driver on and off in a controlled manner, said feedback path providing a bidirectional path through said inherent capacitance for current flow between said control node and said bus to selectively control the voltage level of a signal at said control node and thereby control the rate at which said driver turns on and off in response to said data input signal; and c. a driver pull-down transistor having a drain terminal connected to the control node and a gate terminal controlled by a pull-down control signal complementary to said data input signal to condition the control node to a selected level when the data input signal shifts levels to thereby facilitate a rapid turn-off of the driver transistor.
Claim 8
Dependent Claim
33 words
A bus transmitter circuit as defined in claim 5 further comprising an inverter for receiving said pull-down control signal and producing said data input signal as the complement of said pull-down control signal.
Claim 9
Dependent Claim
155 words
A bus transmitter circuit comprising a driver transistor having an output terminal for connection to a bus line, a reference terminal coupled to a power supply, and an input terminal coupled to a control node, a buffer for controlling the control node of said driver in response to the condition of a data signal received by said buffer to turn said driver transistor on and off in a controlled manner, and an inherent capacitance disposed between said input terminal and said output terminal that is relatively high compared to other capacitances at said input terminal to provide an internal feedback path between said output terminal and said control node for the bidirectional flow of current between said control node and said bus to selectively control the voltage level of a signal at said control node and thereby control the rate at which said driver transistor turns on an doff in response to said data signal.
Claim 10
Dependent Claim
155 words
A bus transmitter circuit comprising a driver transistor having an output terminal for connection to a bus line, a reference terminal coupled to a power supply, and an input terminal coupled to a control node, a buffer for controlling the control node of said driver in response to the condition of a data signal received by said buffer to turn said driver transistor on and off in a controlled manner, and an inherent capacitance disposed between said input terminal and said output terminal that is relatively high compared to other capacitances at said input terminal to provide an internal feedback path between said output terminal and said control node for the bidirectional flow of current between said control node and said bus to selectively control the voltage level of a signal at said control node and thereby control the rate at which said driver transistor turns on an doff in response to said data signal.
Claim 11
Dependent Claim
39 words
The bus transmitter circuit of claim 7 wherein said capacitance is an inherent capacitance of said driver transistor between said input terminal and said output terminal that substantially dominates other capacitances of said driver transistor at said input terminal.
Claim 12
Dependent Claim
29 words
The bus transmitter circuit of claim 8 wherein said driver transistor is a field effect transistor and said input terminal is the gate terminal of said field effect transistor.
Claim 13
Dependent Claim
33 words
The bus transmitter circuit of claim 7 wherein said buffer comprises current source circuitry for controlling current at said control node to turn said driver transistor on and off in a controlled manner.
Claim 14
Dependent Claim
61 words
The bus transmitter circuit of claim 7 further comprising a driver pull-down transistor having an output terminal connected to said control node and an input terminal controlled by a pull-down control signal complementary to said data signal to condition the control node to a selected level when the data signal shifts levels to thereby facilitate rapid turn-off of said driver transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-02 | 1995-06-03 | 1995-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-02 | 1999-06-03 | 1999-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-02 | 2003-06-03 | 2003-12-03 | $7700.00 | Window Closed / Lapsed |