US3772533A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Trapezoidal waveform generator circuit
Assignee: NCR Voyix Corp
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Filing: 1972-06-09
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Granted: 1973-11-13
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Expires: 1992-06-09
Abstract
Abstract There is disclosed a ramp generator responsive to a pulse-type signal for providing an output signal which linearly ramps between two voltage values. The ramp generator includes an operational amplifier integrator circuit and a pair of feedback regulating paths around the integrator circuit to regulate the output voltage values.
Inventors
- 👤 R Bruckner
- 👤 D Rex
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:12
CPC Classifications
H; H03; H03K; H03K4/00; H03K4/94
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
353 words
A circuit which in response to a pulse-type signal provides a voltage which linearly ramps between a first voltage value and a second voltage value in response to the leading edge of said pulse-type signal and which linearly ramps between said second voltage value and said first voltage value in response to the trailing edge of said pulse-type signal, said circuit comprising: inverting amplifying means having an input and an output, said pulse-type signal being applied to said input; capacitance means coupled between said input and said output; first switching means having two terminals respectively direct current coupled to said input and said output, wherein said first switching means includes a solid state device having first and second main electrodes, each coupled respectively to one of said two terminals thereof and a control electrode coupled to a point of first fixed potential, said solid state device of said first switching means allowing current to flow between said output and said input whenever the voltage as said output becomes said first vOltage value; second switching means having two terminals respectively direct current coupled to said input and said output, wherein said second switching means includes a solid state device having first and second main electrodes each coupled respectively to one of said two terminals thereof and a control electrode coupled to a point of second fixed potential, said solid state device of said second switching means allowing current to flow between said input and said output whenever the voltage at said output becomes said second voltage value; wherein said solid state device of said first switching means is a PNP transistor having a base, an emitter and a collector, said base being coupled to said point of first fixed potential, said emitter being coupled to said output, and said collector being coupled to said input; and wherein said solid state device of said second switching means is an NPN transistor having a base, an emitter, and a collector, said base being coupled to said point of second fixed potential, said emitter being coupled to said output, and said collector being coupled to said input.
Claim 2
Dependent Claim
353 words
A circuit which in response to a pulse-type signal provides a voltage which linearly ramps between a first voltage value and a second voltage value in response to the leading edge of said pulse-type signal and which linearly ramps between said second voltage value and said first voltage value in response to the trailing edge of said pulse-type signal, said circuit comprising: inverting amplifying means having an input and an output, said pulse-type signal being applied to said input; capacitance means coupled between said input and said output; first switching means having two terminals respectively direct current coupled to said input and said output, wherein said first switching means includes a solid state device having first and second main electrodes, each coupled respectively to one of said two terminals thereof and a control electrode coupled to a point of first fixed potential, said solid state device of said first switching means allowing current to flow between said output and said input whenever the voltage as said output becomes said first vOltage value; second switching means having two terminals respectively direct current coupled to said input and said output, wherein said second switching means includes a solid state device having first and second main electrodes each coupled respectively to one of said two terminals thereof and a control electrode coupled to a point of second fixed potential, said solid state device of said second switching means allowing current to flow between said input and said output whenever the voltage at said output becomes said second voltage value; wherein said solid state device of said first switching means is a PNP transistor having a base, an emitter and a collector, said base being coupled to said point of first fixed potential, said emitter being coupled to said output, and said collector being coupled to said input; and wherein said solid state device of said second switching means is an NPN transistor having a base, an emitter, and a collector, said base being coupled to said point of second fixed potential, said emitter being coupled to said output, and said collector being coupled to said input.
Claim 3
Dependent Claim
52 words
The invention according to claim 11: wherein said amplifying means is an operational amplifier; and wherein said circuit further includes a first resistor coupled between said input and said output and a second resistor coupled between said input and the terminals of said first and second switching means remote from said output.
Claim 4
Dependent Claim
20 words
The invention according to claim 2 wherein said input signal is applied to said amplifying means through said second resistor.
Claim 5
Dependent Claim
40 words
The invention according to claim 2 wherein the slope of said ramp between said first and second voltage values and between said second and first voltage values is determined by the values of said capacitance means and said second resistor.
Claim 6
Dependent Claim
66 words
The invention according to claim 1 wherein said inverting amplifying means includes first and second resistors and an operational amplifier having an output which is coupled to said amplifying means output and an input, said first resistor being coupled between said operational amplifier input and output, and said second resistor being coupled between said inverting amplifying means input and the inverting input of said operational amplifier.
Claim 7
Dependent Claim
163 words
A circuit comprising: an operational amplifier having an inverting input, a noninverting input, and an output; a capacitor coupled between said output and said inverting input; a first resistor coupled between said output and said inverting input; a second resistor having a first end coupled to said inverting input and further having a second end constituting an input to said circuit; a PNP transistor having a base, an emitter and a collector; means for coupling said emitter to said output; means for coupling said collector to said second end of said second resistor; means for coupling said base to a point of first potential; an NPN transistor having a base, an emitter and a collector; means for coupling said emitter to said output; means for coupling said collector to said second end of said second resistor; means for coupling said base to a point of second potential; and means for applying a pulse type voltage to said second end of said second resistor.
Claim 8
Dependent Claim
163 words
A circuit comprising: an operational amplifier having an inverting input, a noninverting input, and an output; a capacitor coupled between said output and said inverting input; a first resistor coupled between said output and said inverting input; a second resistor having a first end coupled to said inverting input and further having a second end constituting an input to said circuit; a PNP transistor having a base, an emitter and a collector; means for coupling said emitter to said output; means for coupling said collector to said second end of said second resistor; means for coupling said base to a point of first potential; an NPN transistor having a base, an emitter and a collector; means for coupling said emitter to said output; means for coupling said collector to said second end of said second resistor; means for coupling said base to a point of second potential; and means for applying a pulse type voltage to said second end of said second resistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-11-12 | 1977-05-14 | 1977-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-11-12 | 1981-05-14 | 1981-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-11-12 | 1985-05-14 | 1985-11-13 | $7700.00 | Window Closed / Lapsed |