Semiconductor device and method of manufacturing the same

Claim 1

A semiconductor device comprising: (a) a semiconductor substrate; (b) an MOS element formed on a main surface of said semiconductor substrate, and having a buried contact structure; and (c) said buried contact structure including a first contact diffused region formed in said main surface of said semiconductor substrate by diffusion from a polycrystalline silicon layer, and a second contact diffused region formed by diffusion, said second contact diffused region being located deeper in said semiconductor substrate than said first contact diffused region such that said first contact diffused region overlays at least a portion of said second contact diffused region; wherein said first contact diffused region has a depth of diffusion of 0.1 to 0.3 μm and said second contact diffused region has a depth of diffusion of 0.5 to 0.8 μm, and wherein said MOS element comprises a source/drain diffused region, said depth of diffusion of said second contact diffused region being larger than a depth of said source/drain diffused region of said MOS element.

Claim 10

A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a lower contact diffused region in a silicon substrate by forming a field oxide film and a gate oxide film on said silicon substrate and doping said silicon substrate with an impurity of a large diffusion constant to form a buried contact structure forming region in said silicon substrate; (b) forming an upper contact diffused region in said silicon substrate over said lower contact diffused region by forming openings in the gate oxide film, forming a polycrystalline silicon layer on the silicon substrate over said lower contact diffused region and doping said silicon substrate with an impurity of a small diffusion constant into the buried contact structure forming region via the openings such that said upper contact diffused region overlays at least a portion of said lower contact diffused region; (c) etching the polycrystalline silicon layer thereby forming a gate electrode and a source/drain electrode; and (d) doping said silicon substrate with an impurity between said gate electrode and said source/drain electrode thereby forming a source/drain diffused region in said silicon substrate.

Claim 11

A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a lower contact diffused region in a silicon substrate by forming a field oxide film and a gate oxide film on said silicon substrate and doping said silicon substrate with an impurity of a large diffusion constant to form a buried contact structure forming region in said silicon substrate; (b) forming an upper contact diffused region in said silicon substrate over said lower contact diffused region by forming openings in the gate oxide film, forming a polycrystalline silicon layer on the silicon substrate over said lower contact diffused region and doping said silicon substrate with an impurity of a small diffusion constant into the buried contact structure forming region via the openings such that said upper contact diffused region overlays at least a portion of said lower contact diffused region; (c) etching the polycrystalline silicon layer thereby forming a gate electrode and a source/drain electrode; and (d) doping said silicon substrate with an impurity between said gate electrode and said source/drain electrode thereby forming a source/drain diffused region in said silicon substrate.

Claim 20

A method of manufacturing a semiconductor device having a MOS element and a bipolar element on a silicon substrate, the method comprising the steps of: (a) forming a well on said silicon substrate; (b) forming a field oxide film and a gate oxide film on said well; (c) forming a lower contact diffused region of said MOS element and a collector diffused region of said bipolar element in said well by doping said well with an impurity of a large diffusion constant, said lower contact diffused region being part of a buried contact structure forming region of said MOS element; (d) forming an upper contact diffused region of said MOS element over said lower contact diffused region and an emitter diffused region of said bipolar element spaced from said collector diffused region by masking said MOS element, doping said well with an impurity thereby forming a base diffused region of said bipolar element, forming openings in said gate oxide film over said buried contact structure forming region and said base diffused region, forming a polycrystalline silicon layer on said silicon substrate over said lower contact diffused region and said base diffused region, and doping said well with an impurity of a small diffusion constant through said openings in said gate oxide film to form said upper contact diffused region over said lower contact diffused region and said emitter diffused region in said base diffused region such that said upper contact diffused region overlays at least a portion of said lower contact diffused region; (e) forming a gate electrode and a source/drain electrode of said MOS element and an emitter electrode of said bipolar element by etching said polycrystalline layer; and (f) forming a source/drain diffused region in said well by masking said bipolar element and doping said well with an impurity between said gate electrode and said source/drain electrode.

Claim 21

A method of manufacturing a semiconductor device having a MOS element and a bipolar element on a silicon substrate, the method comprising the steps of: (a) forming a well on said silicon substrate; (b) forming a field oxide film and a gate oxide film on said well; (c) forming a lower contact diffused region of said MOS element and a collector diffused region of said bipolar element in said well by doping said well with an impurity of a large diffusion constant, said lower contact diffused region being part of a buried contact structure forming region of said MOS element; (d) forming an upper contact diffused region of said MOS element over said lower contact diffused region and an emitter diffused region of said bipolar element spaced from said collector diffused region by masking said MOS element, doping said well with an impurity thereby forming a base diffused region of said bipolar element, forming openings in said gate oxide film over said buried contact structure forming region and said base diffused region, forming a polycrystalline silicon layer on said silicon substrate over said lower contact diffused region and said base diffused region, and doping said well with an impurity of a small diffusion constant through said openings in said gate oxide film to form said upper contact diffused region over said lower contact diffused region and said emitter diffused region in said base diffused region such that said upper contact diffused region overlays at least a portion of said lower contact diffused region; (e) forming a gate electrode and a source/drain electrode of said MOS element and an emitter electrode of said bipolar element by etching said polycrystalline layer; and (f) forming a source/drain diffused region in said well by masking said bipolar element and doping said well with an impurity between said gate electrode and said source/drain electrode.