Monolithic focal plane array

Claim 2

A single crystalline wafer having first and second surfaces, the wafer having the structural integrity required to survive the fabrication of integrated circuitry upon its first and second surfaces, the wafer comprising: (a) at least one hollow formed in the first surface of the wafer, said hollow having a floor and beveled sides; (b) a plurality of apertures which extend from the floor of each hollow, through the floor of the hollow, to the second surface of the wafer; and (c) wherein the wafer is at least an order of magnitude thicker than the diameter of said apertures.

Claim 3

The wafer as recited in claim 1 further comprising first conductive conduits formed within said apertures, and a corresponding number of second conductive conduits extending along the inclined side walls, said first and second conductive conduits being connected to provide electrical connection between the first and second surfaces of the wafer.

Claim 4

The wafer as recited in claim 2 wherein the first conductive conduits are formed by depositing a refractory conductor within said apertures.

Claim 5

The wafer as recited in claim 3 wherein the beveled sides of the hollows are formed at an angle of approximately 54° to the upper and lower surfaces.

Claim 6

The wafer as recited in claim 3 wherein the apertures are formed by etching.

Claim 7

The wafer as recited in claim 3 wherein the apertures are formed by laser drilling.

Claim 8

A detector interface board for facilitating electrical communication between circuitry disposed upon a first surface of the board and an array of detector elements disposed upon an opposing second surface of the board, the board comprising: (a) a wafer comprising at least one hollow having a floor and beveled side walls formed in the first surface of the wafer; (b) a plurality of apertures formed through the floor of each hollow, the apertures extending from the floor of each hollow to the wafer second surface; (c) a plurality of first conductive conduits formed within each of the apertures; (d) a corresponding number of second conductive conduits which extend along the hollow sidewalls from the apertures; (e) a body of polysilicon formed within each of said hollows; (f) a single crystalline layer formed upon the wafer first surface; (g) a plurality of third conductive conduits formed upon the wafer second surface, each of said third conductive conduits being connected to a dedicated aperture; (h) a single crystalline layer graphotaxially formed upon the wafer second surface; (i) an array of detector elements formed upon the single crystalline layer of the wafer second surface, each of said detector elements being connected to a dedicated aperture by the third conductive conduits; and (j) signal processing circuitry formed upon the single crystalline layer, said signal processing circuitry being connected to the first conductive conduits.

Claim 9

A detector interface board for facilitating electrical communication between circuitry disposed upon a first surface of the board and an array of detector elements disposed upon an opposing second surface of the board, the board comprising: (a) a wafer comprising at least one hollow having a floor and beveled side walls formed in the first surface of the wafer; (b) a plurality of apertures formed through the floor of each hollow, the apertures extending from the floor of each hollow to the wafer second surface; (c) a plurality of first conductive conduits formed within each of the apertures; (d) a corresponding number of second conductive conduits which extend along the hollow sidewalls from the apertures; (e) a body of polysilicon formed within each of said hollows; (f) a single crystalline layer formed upon the wafer first surface; (g) a plurality of third conductive conduits formed upon the wafer second surface, each of said third conductive conduits being connected to a dedicated aperture; (h) a single crystalline layer graphotaxially formed upon the wafer second surface; (i) an array of detector elements formed upon the single crystalline layer of the wafer second surface, each of said detector elements being connected to a dedicated aperture by the third conductive conduits; and (j) signal processing circuitry formed upon the single crystalline layer, said signal processing circuitry being connected to the first conductive conduits.

Claim 10

The detector interface board as recited in claim 7 further comprising: (a) a first insulator, said first insulator coating both the first and second surfaces of the wafer; (b) a second insulator, said second insulator coating a portion of the first surface of the wafer including said second conductive conduits, to insulate said second conductive conduits from subsequent layers; (c) a third insulator, said third insulator coating a portion of the first surface of the wafer including the body of polysilicon formed within each of said hollows to insulate the body of polysilicon from subsequent layers; and (d) a fourth insulator, said fourth insulator coating a portion of the second surface of the wafer including said third conductive conduits formed upon the second surface of the wafer to insulate said third conductive conduits from subsequent layers.

Claim 11

The detector interface board as recited in claim 7 wherein HgCdTe is used to form the array of detector elements.

Claim 12

The detector interface board as recited in claim 7 wherein the array of detector elements are formed graphotaxially directly upon said single crystalline layer formed upon the second surface of the wafer.

Claim 13

The detector interface board as recited in claim 7 wherein the array of detector elements are formed upon a layer of gallium arsenide which is formed upon said single crystalline layer formed upon the second surface of the wafer.

Claim 14

The detector interface board as recited in claim 7 wherein the first conductive conduits are formed by depositing a refractory conductor within said apertures.

Claim 15

The detector interface board as recited in claim 7 wherein the beveled sides of the hollows are formed at an angle of approximately 54° to the upper and lower surfaces.

Claim 16

The detector interface board as recited in claim 7 wherein the apertures are formed by etching.

Claim 17

The detector interface board as recited in claim 7 wherein the apertures are formed by laser drilling.