RF amplitude modulator/mixer

Claim 3

The method as recited in claim 1 wherein the step of adjusting the amplitude of the DC bias signal comprises adjusting the amplitude to a level corresponding to the highest obtainable percent modulation of the carrier signal obtainable from the dual balanced modulator.

Claim 4

The method as recited in claim 1 wherein the step of adjusting the amplitude of the DC bias signal comprises biasing the modulating signal to a DC level producing between 50 and 100 percent amplitude modulation of the carrier signal from the dual balanced modulator.

Claim 5

The method as recited in claim 1 wherein the step of adjusting the amplitude of the DC bias signal comprises biasing the carrier to compensate for attenuation of the carrier signal with respect to carrier sidebands in the output of the dual balanced modulator.

Claim 6

The method as recited in claim 4 wherein the step of biasing the carrier to a level to compensate for attenuation of the carrier with respect to the sideband comprises biasing the carrier to compensate for high frequency effects of electrical components used to isolate the modulating signal input and the bias level input.

Claim 7

The method as recited in claim 1 further comprising the step of electrically blocking signals at each of said first and second inputs to said offset circuit from reaching the other of said first and second inputs.

Claim 8

The method as recited in claim 1 wherein the step of providing a high speed modulating signal comprises providing a modulating signal of at least 30 MHz.

Claim 9

The method as recited in claim 1 wherein the step of providing a high frequency carrier signal comprises providing a carrier signal of at least 2.06 GHz.

Claim 10

An offset circuit for adjusting the DC level of a modulating signal input to a dual balanced modulator comprising: (a) a first port for receiving a modulating signal; (b) a second port for receiving a DC bias signal; (c) coupling circuitry connected to said first and second ports for offsetting the modulating signal received at said first port by a voltage level responsive to the DC bias signal received at said second port, said coupling circuit having an output connectable with a modulation signal input to a dual balanced mixer; and (d) said DC voltage being selected to a voltage regulator for varying the amplitude of the DC bias signal in order to amplitude modulate the carrier signal output from the dual balanced modulator to an optimum percent modulation level.

Claim 11

An offset circuit for adjusting the DC level of a modulating signal input to a dual balanced modulator comprising: (a) a first port for receiving a modulating signal; (b) a second port for receiving a DC bias signal; (c) coupling circuitry connected to said first and second ports for offsetting the modulating signal received at said first port by a voltage level responsive to the DC bias signal received at said second port, said coupling circuit having an output connectable with a modulation signal input to a dual balanced mixer; and (d) said DC voltage being selected to a voltage regulator for varying the amplitude of the DC bias signal in order to amplitude modulate the carrier signal output from the dual balanced modulator to an optimum percent modulation level.

Claim 12

The circuit as recited in claim 9 further comprising a blocking capacitor connected to said first port and adapted to block DC signals from reaching said second port.

Claim 13

The offset circuit as recited in claim 9 further comprising a first inductor connected between said first and second ports and a shorting capacitor connected to said second port, said first inductor and said shorting capacitor being adapted to opposed transmission of said modulating signal to said second port.