Patent US5311470A successfully refreshed from Google Patents.
US5311470A
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Data latch circuit having non-volatile memory cell
Assignee: Toshiba Corp
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Filing: 1992-07-24
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Granted: 1994-05-10
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Expires: 2012-07-24
Abstract
Abstract A data latch circuit comprises a non-volatile memory cell having its threshold voltage changed in accordance with data to be stored therein, and a latch circuit. The cell has a transistor for writing data and a transistor for reading data. The writing and reading transistors has a common floating gate. The reading transistor has a threshold voltage lower than the writing transistor. During normal operation, a ground potential is applied to the control gate of the reading transistor. The latch circuit latches data in accordance with whether the non-volatile memory cell is in the on-state or off-state.
Inventors
- 👤 Shigeru Atsumi
- 👤 Hironori Banba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:48
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C29/789; G06; G06F; G06F11/00; G06F11/006; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C8/00; G11C8/06; G11C29/781
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
195 words
A data latch circuit comprising: a first non-volatile memory cell having a first writing transistor and a first reading transistor, and disposed to store data, the first writing transistor and reading transistor having at least one first control gate and a first common floating gate, the first reading transistor having a threshold voltage lower than the first writing transistor, the control gate of the first reading transistor being disposed to be supplied, during normal operation, with a constant voltage independent from a power supply voltage; a second non-volatile memory cell having a second writing transistor and a second reading transistor, and disposed to store complementary data with respect to data to be stored in the first non-volatile memory cell, the second writing and reading transistors having at least one second control gate and a second common floating gate, the second reading transistor having a threshold voltage lower than the second writing transistor, the control gate of the second reading transistor being disposed to be supplied, during normal operation, with the constant voltage; and latch means for latching potentials corresponding to the on- and off-states of the first non-volatile memory cell and second non-volatile memory cell.
Claim 2
Dependent Claim
195 words
A data latch circuit comprising: a first non-volatile memory cell having a first writing transistor and a first reading transistor, and disposed to store data, the first writing transistor and reading transistor having at least one first control gate and a first common floating gate, the first reading transistor having a threshold voltage lower than the first writing transistor, the control gate of the first reading transistor being disposed to be supplied, during normal operation, with a constant voltage independent from a power supply voltage; a second non-volatile memory cell having a second writing transistor and a second reading transistor, and disposed to store complementary data with respect to data to be stored in the first non-volatile memory cell, the second writing and reading transistors having at least one second control gate and a second common floating gate, the second reading transistor having a threshold voltage lower than the second writing transistor, the control gate of the second reading transistor being disposed to be supplied, during normal operation, with the constant voltage; and latch means for latching potentials corresponding to the on- and off-states of the first non-volatile memory cell and second non-volatile memory cell.
Claim 3
Dependent Claim
16 words
The data latch circuit according to claim 1, wherein the latch means includes a flip-flop circuit.
Claim 4
Dependent Claim
76 words
The data latch circuit according to claim 2, wherein the flip-flop circuit includes first p-channel MOS transistor and second p-channel MOS transistor, the first p-channel MOS transistor having a gate connected to the drain of the second p-channel MOS transistor, and a drain connected to the gate of the second p-channel MOS transistor, the first p-channel MOS transistor and second p-channel MOS transistor serving as the loads of first reading transistor and second reading transistor, respectively.
Claim 5
Dependent Claim
107 words
The data latch circuit according to claim 3, further comprising: a first stress-relaxing transistor having a current path, one end of which is connected to an end of the current path of the first reading transistor, and the other end of which is connected to the first p-channel MOS transistor, and a gate connected to a ground terminal; and a second stress-relaxing transistor having a current path, one end of which is connected to an end of the current path of the second reading transistor, and the other end of which is connected to the second p-channel MOS transistor, and a gate connected to the ground terminal.
Claim 6
Dependent Claim
133 words
The data latch circuit according to claim 1, further comprising: a first write control transistor which has a current path connected between the drain of the first writing transistor and a power supply used for writing, and also has a gate to be supplied with a power supply voltage for writing at the time of writing and to be supplied with a ground potential at the time of other than writing; and a second write control transistor which has a current path connected between the drain of the second writing transistor and the power supply used for writing, and also has a gate to be supplied with the power supply voltage for writing at the time of writing and to be supplied with the ground potential at the time of other than writing.
Claim 7
Dependent Claim
35 words
The data latch circuit according to claim 1, further comprising selector means responsive to the output of the latch means for selecting one of an address signal and an inverted signal of the address signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-09 | 1997-11-08 | 1998-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-09 | 2001-11-08 | 2002-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-09 | 2005-11-08 | 2006-05-10 | $7700.00 | Window Closed / Lapsed |