Data processing apparatus having address decoder supporting wide range of operational frequencies

Claim 2

A data processing system operable at a predetermined system frequency including an addressable device, an address bus for transmitting address signals to said device, and a decoder connected between said address bus and said device for decoding unlatched address signals directed to said addressable device, said decoder comprising: latch means having first inputs connected to receive unlatched address signals from said address bus and a second input for receiving a clock signal for latching addresses on said first inputs into said latch means, said latch means outputting latched address signals; decoding means comprising first and second decode logic circuits, said first decode logic circuit having an input connected to received unlatched address signals from said address bus and produce an unlatched decode signal, said second decode logic circuit being connected to receive latched address signals from said latch means and produce a latched decode signal; a multiplexer connected to receive said decode signals from said decode logic circuits, said multiplexer receiving a binary control input where said decoder is selectively operable in a latched mode of operation and in an unlatched mode of operation; and control means connected to said multiplexer generating said binary control input selectively settable to two values, one value causing said decoding means to produce an unlatched decode signal based on said unlatched address signals when said system frequency is below a predetermined frequency, and another value causing said decoding means to produce a latched decode signal based on said latched address signals when said system frequency is above said predetermined frequency.

Claim 3

A data processing system operable at a predetermined system frequency including an addressable device, an address bus for transmitting address signals to said device, and a decoder connected between said address bus and said device for decoding unlatched address signals directed to said addressable device, said decoder comprising; latch means having first inputs connected to receive unlatched address signals from said address bus and a second input for receiving a clock signal for latching addresses on said first inputs into said latch means, said latch means outputting latched address signals; decoding means connected to said address bus and to said latch means for receiving both said latched address signals from said latch means and said unlatched address signals from said address bus and producing a decode signal derived from said unlatched address signal in said unlatched mode and from said latched address signal in said latched mode where said decoder is selectively operable in a latched mode of operation and in an unlatched mode of operation; and control means connected to said decoding means generating and comprising a binary control input set automatically in accordance with said system frequency selectively settable to two values, one value causing said decoding means to produce an unlatched decode signal based on said unlatched address signals when said system frequency is below a predetermined frequency, and another value causing said decoding means to produce a latched decode signal based on said latched address signals when said system frequency is above said predetermined frequency.

Claim 4

A data processing system operable at a predetermined system frequency including an addressable device, an address bus for transmitting address signals to said device, and a decoder connected between said address bus and said device for decoding unlatched address signals directed to said addressable device, said decoder comprising; latch means having first inputs connected to receive unlatched address signals from said address bus and a second input for receiving a clock signal for latching addresses on said first inputs into said latch means, said latch means outputting latched address signals; decoding means connected to said address bus and to said latch means for receiving both said latched address signals from said latch means and said unlatched address signals from said address bus and producing a decode signal derived from said unlatched address signal in said unlatched mode and from said latched address signal in said latched mode where said decoder is selectively operable in a latched mode of operation and in an unlatched mode of operation; and control means connected to said decoding means generating and comprising a binary control input set automatically in accordance with said system frequency selectively settable to two values, one value causing said decoding means to produce an unlatched decode signal based on said unlatched address signals when said system frequency is below a predetermined frequency, and another value causing said decoding means to produce a latched decode signal based on said latched address signals when said system frequency is above said predetermined frequency.

Claim 5

A data processing system in accordance with claim 2 comprising: a comparator for comparing said system frequency with a predetermined breakdown frequency and setting said binary control input in accordance with such comparison.

Claim 6

A data processing system operable at a predetermined system frequency including an addressable device, an address bus for transmitting address signals to said device, and a decoder connected between said address bus and said device for decoding unlatched address signals directed to said addressable device, said decoder comprising: latch means having first inputs connected to receive unlatched address signals from said address bus and a second input for receiving a clock signal for latching addresses on said first inputs into said latch means, said latch means outputting latched address signals; decoding means connected to said address bus and to said latch means for receiving both said latched address signals from said latch means and said unlatched address signals from said address bus and producing a decode signal derived from said unlatched address signal in said unlatched mode and from said latched address signal in said latched mode where said decoder is selectively operable in a latched mode of operation and in an unlatched mode of operation; and selectively actuated mode control means for operating said decoder in one of said modes of operation so as to allow said decoder to be operated in said unlatched mode when said system frequency is below a predetermined value and in said latched mode when said system frequency is above said predetermined value.

Claim 7

A data processing system operable at a predetermined system frequency including an addressable device, an address bus for transmitting address signals to said device, and a decoder connected between said address bus and said device for decoding unlatched address signals directed to said addressable device, said decoder comprising: latch means having first inputs connected to receive unlatched address signals from said address bus and a second input for receiving a clock signal for latching addresses on said first inputs into said latch means, said latch means outputting latched address signals; decoding means connected to said address bus and to said latch means for receiving both said latched address signals from said latch means and said unlatched address signals from said address bus and producing a decode signal derived from said unlatched address signal in said unlatched mode and from said latched address signal in said latched mode where said decoder is selectively operable in a latched mode of operation and in an unlatched mode of operation; and selectively actuated mode control means for operating said decoder in one of said modes of operation so as to allow said decoder to be operated in said unlatched mode when said system frequency is below a predetermined value and in said latched mode when said system frequency is above said predetermined value.

Claim 8

A data processing system operable at a predetermined system frequency, including a system clock signal operable at a predetermined frequency, an addressable state machine, an address bus for transmitting address signals to access said state machine in synchronism with said system clock signal and a decoder connected between said address bus and said state machine for decoding unlatched address signals directed to said addressable state machine, comprising: a plurality of latches within the decoder connected to said address bus for temporarily storing address signals therein in synchronism with the operation of said bus and said state machine; decoding means connected to said address bus and to said latches for producing a decode signal when said address signals are directed to said state machine, said decoding means being selectively operable in a latched mode of operation and in an unlatched mode of operation whereby said decode signal is derived from said address signals stored in said latches in said latched mode of operation and from address signals on said bus when in said unlatched mode of operation; control means responsive to a SELECT signal to operate said decoding means in one of said modes; and the state machine having an idle state, a wait state, and an operations state during which said state machine performs an operation for which said state machine is being accessed, said state machine being operable in response to a STROBE signal and to said decode signal to switch from said idle state to said operations state when in said unlatched mode of operation and to switch from said idle state to said wait state and then to said operations state when in said latched mode of operation.

Claim 9

A data processing system operable at a predetermined system frequency, including a system clock signal operable at a predetermined frequency, an addressable state machine, an address bus for transmitting address signals to access said state machine in synchronism with said system clock signal and a decoder connected between said address bus and said state machine for decoding unlatched address signals directed to said addressable state machine, comprising: a plurality of latches within the decoder connected to said address bus for temporarily storing address signals therein in synchronism with the operation of said bus and said state machine; decoding means connected to said address bus and to said latches for producing a decode signal when said address signals are directed to said state machine, said decoding means being selectively operable in a latched mode of operation and in an unlatched mode of operation whereby said decode signal is derived from said address signals stored in said latches in said latched mode of operation and from address signals on said bus when in said unlatched mode of operation; control means responsive to a SELECT signal to operate said decoding means in one of said modes; and the state machine having an idle state, a wait state, and an operations state during which said state machine performs an operation for which said state machine is being accessed, said state machine being operable in response to a STROBE signal and to said decode signal to switch from said idle state to said operations state when in said unlatched mode of operation and to switch from said idle state to said wait state and then to said operations state when in said latched mode of operation.

Claim 10

A data processing system in accordance with claim 5 wherein: said decoding means has a circuit delay time sufficiently short relative to said system frequency so as to allow said decode signal to be generated within one system clock period so as to allow said state machine to be switched into said operations state in a clock period immediately following said one period, when in said unlatched mode of operation.

Claim 11

A data processing system in accordance with claim 5 wherein: said decoding means has a circuit delay time relatively long relative to said system frequency whereby said state machine is switched from idle state to said wait state in a first clock period, said decode signal is generated within a second clock period following said first clock period so as to allow said state machine to be switched into said operations state in a third clock period immediately following said second period, when in said latched mode of operation.