Zero fall-through time asynchronous fifo buffer with nonambiguous empty-full resolution

Claim 3

The method of claim 1 further including the step of initiating a memory operation on a transitional edge of an electrical pulse directed to said memory by other equipment, and completing said memory operation as a result of said transitional edge irrespective of any other transitional edge of said electrical pulse.

Claim 4

The method of claim 2 further including the step of generating a second electrical pulse within said memory system for reading said memory as a result of said transitional edge.

Claim 5

The method of claim 3 further including the step of generating a third electrical pulse within said memory system for writing said memory as a result of said transitional edge.

Claim 6

The method of claim 3 further including the step of inhibiting the generation of the second electrical pulse for reading the memory when said indication indicates the memory is empty.

Claim 7

The method of claim 4 further including inhibiting the generation of the third electrical pulse for writing the memory when said indication indicates the memory is full.

Claim 8

In a shift register memory system, a circuit for determining the status thereof, comprising: (a) means for maintaining an account of the last memory read and write operations in said memory system; (b) means for comparing the current address of a memory write operation with the current address of a memory read operation; and (c) means for providing an indication of the status of said memory system upon the equality of the current address of a memory read operation with respect to the current address of a memory write operation wherein: i. the status of said memory is determined as being full when the last memory operation was a write operation, and ii. the status of said memory is determined as being empty when said last memory operation was a read operation.

Claim 9

In a shift register memory system, a circuit for determining the status thereof, comprising: (a) means for maintaining an account of the last memory read and write operations in said memory system; (b) means for comparing the current address of a memory write operation with the current address of a memory read operation; and (c) means for providing an indication of the status of said memory system upon the equality of the current address of a memory read operation with respect to the current address of a memory write operation wherein: i. the status of said memory is determined as being full when the last memory operation was a write operation, and ii. the status of said memory is determined as being empty when said last memory operation was a read operation.

Claim 10

The circuit of claim 7 further including: means for initiating a memory operation on a transitional edge of one of a plurality of input electrical pulses directed to said memory by other equipment; and means for completing said memory operation as a result of said transitional edge irrespective of other transitional edges of said plurality of input electrical pulses.

Claim 11

The circuit of claim 8 further including means responsive to said transitional edge for generating a second electrical pulse for reading said memory.

Claim 12

The circuit of claim 8 further including means responsive to said transitional edge for generating a second electrical pulse for writing said memory.

Claim 13

The circuit of claim 9 further including means for inhibiting the generation of the second electrical pulse for reading said memory when said memory is empty.

Claim 14

The circuit of claim 10 further including means for inhibiting the generation of the second electrical pulse for writing said memory when said memory is full.

Claim 15

In a memory of the type having a plurality of interconnected addressable memory registers responsive to memory operations for writing data therein and reading data therefrom, a read and write controller, comprising: write address means for sequentially addressing each said memory register for writing data therein; read address means for sequentially addressing each said memory register for reading data therefrom; comparator means for comparing an address of said write address means with an address of said read address means to determine equality of said addresses; read and write storage means for storing an indication of the most recent of a read or write operation of said memory; and means for preventing a memory operation of said memory when said comparator determines equality of said read and write addresses and when said read and write storage means has stored therein an indication that the last memory operation was a predetermined operation of said memory.

Claim 16

In a memory of the type having a plurality of interconnected addressable memory registers responsive to memory operations for writing data therein and reading data therefrom, a read and write controller, comprising: write address means for sequentially addressing each said memory register for writing data therein; read address means for sequentially addressing each said memory register for reading data therefrom; comparator means for comparing an address of said write address means with an address of said read address means to determine equality of said addresses; read and write storage means for storing an indication of the most recent of a read or write operation of said memory; and means for preventing a memory operation of said memory when said comparator determines equality of said read and write addresses and when said read and write storage means has stored therein an indication that the last memory operation was a predetermined operation of said memory.

Claim 17

The memory of claim 13 wherein said write address means further includes: a write address counter; a data input latch for storing input data to be written into one said memory register associated with said write address; and circuit means responsive to the first transition of a write command from an external source for incrementing said write address counter, for latching input data into said latches, and for storing the latched input data in said memory register.

Claim 18

The memory of claim 14 wherein said circuit means further includes pulse generation means responsive to said transition for generating a write pulse for writing said latches input data into said memory registers.

Claim 19

The memory of claim 15 wherein said pulse generation means generates a pulse of predetermined width.

Claim 20

The memory of claim 13 wherein said read address means further includes: a read address counter; and circuit means responsive to the first transition of a read command from an external source for incrementing said read address counter, and reading data from one said memory register.

Claim 21

The memory of claim 14 wherein said circuit means further includes pulse generation means responsive to said transition for generating a read pulse for reading data from said memory register.

Claim 22

The memory of claim 15 wherein said pulse generation means generates a pulse of a predetermined width.

Claim 23

A shift register system, comprising: a memory having a plurality of storage elements each adapted for writing data therein and reading data therefrom; a write address ring counter having a plurality of one-bit stages each with an output connected to a different said storage element for effecting a memory write operation thereof, each said stage further including an input connected to the output of an adjacent stage, and a clock input whereby when clocked the contents of each said stage is transferred to the adjacent stage connected therewith; a read address ring counter having a plurality of one-bit stages each with an output connected to a different said storage element for effecting a memory read operation thereof, each said stage further including an input connected to the output of an adjacent stage, and a clock input whereby when clocked the contents of each said stage are transferred to the adjacent stage connected therewith; means for initializing said write address ring counter and said read address counter so that a logic signal of one level is stored in only one stage of each said counter, and so that a logic signal of another level is stored in the remaining stages of each said counter; a comparator comprising a plurality of logic gates, each said gate having an input connected to the output of one said write address ring counter stage and an input connected to the output of one said read address ring counter shape, the outputs of said logic gates providing an indication of when a storage element of said memory is connected to a write and read address ring counter stage with the outputs thereof having said one logic signal level; a write signal generator responsive to the leading edge transition of an input write command for producing a write pulse to effect a write operation of said memory; a read signal generator responsive to the leading edge transition of an input read command for producing a read pulse to effect a read operation of said memory; a last read/write operation circuit with an input responsive to said write pulse and an input responsive to said read pulse, and an output for indicating the last read or write operation processed by said shift register system; a write enable latch responsive to said indication on the outputs of said comparator logic gates, and responsive to an output of said last read/write operation circuit indicating a write operation last processed, for inhibiting a write operation of said m emory by said write pulse; and a read enable latch responsive to said indication on the outputs of said comparator logic gates, and responsive to an output of said last read/write operation circuit indicating a read operation last processed, for inhibiting a read operation of said memory by said read pulse.

Claim 24

A shift register system, comprising: a memory having a plurality of storage elements each adapted for writing data therein and reading data therefrom; a write address ring counter having a plurality of one-bit stages each with an output connected to a different said storage element for effecting a memory write operation thereof, each said stage further including an input connected to the output of an adjacent stage, and a clock input whereby when clocked the contents of each said stage is transferred to the adjacent stage connected therewith; a read address ring counter having a plurality of one-bit stages each with an output connected to a different said storage element for effecting a memory read operation thereof, each said stage further including an input connected to the output of an adjacent stage, and a clock input whereby when clocked the contents of each said stage are transferred to the adjacent stage connected therewith; means for initializing said write address ring counter and said read address counter so that a logic signal of one level is stored in only one stage of each said counter, and so that a logic signal of another level is stored in the remaining stages of each said counter; a comparator comprising a plurality of logic gates, each said gate having an input connected to the output of one said write address ring counter stage and an input connected to the output of one said read address ring counter shape, the outputs of said logic gates providing an indication of when a storage element of said memory is connected to a write and read address ring counter stage with the outputs thereof having said one logic signal level; a write signal generator responsive to the leading edge transition of an input write command for producing a write pulse to effect a write operation of said memory; a read signal generator responsive to the leading edge transition of an input read command for producing a read pulse to effect a read operation of said memory; a last read/write operation circuit with an input responsive to said write pulse and an input responsive to said read pulse, and an output for indicating the last read or write operation processed by said shift register system; a write enable latch responsive to said indication on the outputs of said comparator logic gates, and responsive to an output of said last read/write operation circuit indicating a write operation last processed, for inhibiting a write operation of said m emory by said write pulse; and a read enable latch responsive to said indication on the outputs of said comparator logic gates, and responsive to an output of said last read/write operation circuit indicating a read operation last processed, for inhibiting a read operation of said memory by said read pulse.

Claim 25

The shift register system of claim 20 further including means responsive to the outputs of said comparator logic gates for signaling an almost full and an almost empty status of said memory.

Claim 26

The shift register system of claim 20 further including means for indicating a full memory condition and an empty memory condition in response respectively to the signaling of said almost full and almost empty statuses.