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Fast IEEE double precision reciprocals and square roots

Assignee: International Business Machines Corp
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Filing: 1993-04-23
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Granted: 1994-04-19
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Expires: 2013-04-23
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Abstract

Abstract A method and apparatus implement reciprocal and square root calculations using Chebyshev polynomial approximation by scaling the mantissas of IEEE floating point numbers based on splitting them into intervals, thereby allowing Chebyshev polynomials of few terms to approximate each interval and resulting in high performance. A reciprocal or square root operation is implemented in a floating point unit (FPU) of a computer having a pipelined multiply accumulate function using a Chebyshev polynomial approximation. A plurality of Chebyshev coefficients are stored in read only storage. Mantissas m of floating point numbers are scaled based on splitting the mantissas into 2 n intervals i as: m'=2N×m-(2N+2i+1), where m' is the scaled mantissa and N is a power of 2. Using a predetermined number of high bits of the scaled mantissa, a set of stored coefficients are read from read only storage to compute the polynomial. The actual computation of the reciprocal or square root is performed by a plurality of multiply accumulates in the piplined function of the FPU to compute the polynomial approximation of the function f(m), which approximation differs from a correct answer by no more than 1 bit: f(m)=c.sub.0 +m'×(c.sub.1 +m'×(c.sub.2 +m'×(c.sub.3 + . . . +m'×c n ))), where c 0 . . . c n are the set of coefficients selected by the high bits of the mantissa. In addition, the method and apparatus distinguish approximations potentially requiring one bit error correction from those known to be correct.

Inventors

  • 👤 Lawrence M. Ammann

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 22:21
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/535; G06F7/544; G06F7/552; G06F7/5525; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/027; G06F2207/00; G06F2207/535; G06F2207/5355; G06F2207/5356; G06F7/483; G06F7/487; G06F7/4873; G06F7/499; G06F7/49942; G06F7/49947; G06F7/49957

Claims Analysis

Total Claims: 21
Claim 1
Independent Claim 204 words
A floating point unit (FPU) in a computer for calculating a mathematical function f(m), where f(m) is a reciprocal or square root function, said FPU having a pipelined multiply accumulate function and further comprising: read only memory (ROM) for storing a plurality of Chebyshev coefficients; scaling logic means for scaling mantissas m' of floating point numbers, said mantissas m being scaled based on splitting the mantissas into 2 n intervals i, thereby allowing Chebyshev polynomials of few terms to approximate each interval, as: m'=2N×m-(2N+2i+1), where N is a power of 2; addressing means responsive to said scaling logic for selecting a set of stored coefficients from said read only memory to compute the polynomial using a predetermined number of high bits of a mantissa, a selected set of coefficients being supplied to said FPU; and said FPU performing a plurality of multiply accumulates using said multiply accumulate function to compute the polynomial approximation of the function f(m), which approximation differs from a correct answer by no more than 1 bit: f(m)=c.sub.0 +m'×(c.sub.1 +m'×(c.sub.2 +m'×(c.sub.3 + . . . +m'×c.sub.n))), where c 0 . . . c n are the set of coefficients selected by the addressing means using the high bits of the mantissa.
Claim 2
Dependent Claim 204 words
A floating point unit (FPU) in a computer for calculating a mathematical function f(m), where f(m) is a reciprocal or square root function, said FPU having a pipelined multiply accumulate function and further comprising: read only memory (ROM) for storing a plurality of Chebyshev coefficients; scaling logic means for scaling mantissas m' of floating point numbers, said mantissas m being scaled based on splitting the mantissas into 2 n intervals i, thereby allowing Chebyshev polynomials of few terms to approximate each interval, as: m'=2N×m-(2N+2i+1), where N is a power of 2; addressing means responsive to said scaling logic for selecting a set of stored coefficients from said read only memory to compute the polynomial using a predetermined number of high bits of a mantissa, a selected set of coefficients being supplied to said FPU; and said FPU performing a plurality of multiply accumulates using said multiply accumulate function to compute the polynomial approximation of the function f(m), which approximation differs from a correct answer by no more than 1 bit: f(m)=c.sub.0 +m'×(c.sub.1 +m'×(c.sub.2 +m'×(c.sub.3 + . . . +m'×c.sub.n))), where c 0 . . . c n are the set of coefficients selected by the addressing means using the high bits of the mantissa.
Claim 3
Dependent Claim 76 words
The FPU according to claim 1 wherein sixty-four bits are used to store a double precision floating point number, comprising one bit for a sign, eleven bits for an exponent, and fifty-two bits for a mantissa, and wherein the function f(m) is a reciprocal (RCIP(x)) and the mantissas are scaled based on ten high bits of the mantissa, said ten high bits being used by said addressing means to select one of 1024 sets of coefficients.
Claim 4
Dependent Claim 79 words
The FPU according to claim 1 wherein sixty-four bits are used to store a double precision floating point number, comprising one bit for a sign, eleven bits for an exponent, and fifty-two bits for a mantissa, and wherein the function f(m) is a square root (SQRT(x)) and the mantissas are scaled based on nine high bits of the mantissa, said nine high bits plus one being used by said addressing means to select one of 1024 sets of coefficients.
Claim 5
Dependent Claim 82 words
The FPU according to claim 1 wherein sixty-four bits are used to store a double precision floating point number, comprising one bit for a sign, eleven bits for an exponent, and fifty-two bits for a mantissa, and wherein the function f(m) is a reciprocal of a square root (1/SQRT(x)) and the mantissas are scaled based on nine high bits of the mantissa, said nine high bits plus one being used by said addressing means to select one of 1024 sets of coefficients.
Claim 6
Dependent Claim 124 words
The FPU according to claim 1 wherein a reciprocal (RCIP(x)) is being computed and the multiply accumulate function generates n extra bits more than is allotted to the mantissa when computing the polynomial approximation of the reciprocal function, further comprising: detecting means for detecting a bit pattern in the n extra bits of 01111 . . . (i.e., 0 followed by n-1 1s), this bit pattern signifying that the mantissa is potentially 1 bit less than required and should be compared to a result with an incremented mantissa; error computation means for computing the error, 1-x×y, where y is an approximation to rcip(x); comparing means for comparing the computed error, 1-x×y, to 1-x×(y+2 -53 ); and means for selecting a result with less error.
Claim 7
Dependent Claim 32 words
An FPU according to claim 5 wherein if the compared results in the comparing means have equal errors, then said means for selecting selects a result with a low bit of 0.
Claim 8
Dependent Claim 133 words
An FPU according to claim 1 wherein a square root (SQRT(x)) is being computed and the multiply accumulate function generates n extra bits more than is allotted to the mantissa when computing the polynomial approximation of the square root function, further comprising: detecting means for detecting if a bit pattern in the n extra bits is 01111 . . . (i.e., 0 followed by n-1 1s), this bit pattern signifying that the mantissa is potentially 1 bit less than required and should be compared to a result with an incremented mantissa; error computation means for computing the error, x-y 2 , where y is the approximation to sqrt(x); comparing means for comparing the computed error, x-y 2 , to x-(y+2 -52 ) 2 ; and means for selecting a result with less error.
Claim 9
Dependent Claim 32 words
An FPU according to claim 7 wherein if the compared results in the comparing means have equal errors, then said means for selecting selects a result with a low bit of 0.
Claim 10
Dependent Claim 124 words
The FPU according to claim 1 wherein a reciprocal (RCIP(x)) is being computed and the multiply accumulate function generates n extra bits more than is allotted to the mantissa when computing the polynomial approximation of the reciprocal function, further comprising: detecting means for detecting a bit pattern in the n extra bits of 10000 . . . (i.e., 1 followed by n-1 0s), this bit pattern signifying that the mantissa is potentially 1 bit more than required and should be compared to a result with a decremented mantissa; error computation means for computing the error, 1-x×y, where y is an approximation to rcip(x); comparing means for comparing the computed error, 1-x×y, to 1-x×(y-2 -53 ); and means for selecting a result with less error.
Claim 11
Dependent Claim 32 words
An FPU according to claim 9 wherein if the compared results in the comparing means have equal errors, then said means for selecting selects a result with a low bit of 0.
Claim 12
Dependent Claim 133 words
An FPU according to claim 1 wherein a square root (SQRT(x)) is being computed and the multiply accumulate function generates n extra bits more than is allotted to the mantissa when computing the polynomial approximation of the square root function, further comprising: detecting means for detecting if a bit pattern in the n extra bits is 10000 . . . (i.e., 1 followed by n-1 0s), this bit pattern signifying that the mantissa is potentially 1 bit more than required and should be compared to a result with a decremented mantissa; error computation means for computing the error, x-y 2 , where y is the approximation to sqrt(x); comparing means for comparing the computed error, x-y 2 , to x-(y-2 -52 ) 2 ; and means for selecting a result with less error.
Claim 13
Dependent Claim 32 words
An FPU according to claim 11 wherein if the compared results in the comparing means have equal errors, then said means for selecting selects a result with a low bit of 0.
Claim 14
Dependent Claim 121 words
An FPU according to claim 1 wherein a reciprocal (RCIP(x)) is being computed and the multiply accumulate function generates n extra bits more than is allotted to the mantissa when computing the polynomial approximation of the reciprocal function, further comprising: detecting means for detecting a bit pattern in the n extra bits of 11111 . . . (i.e., n 1s), this bit pattern signifying that the mantissa is potentially 1 bit less than required and should be compared to a result with an incremented mantissa; error computation means for computing an error, 1-x×y, where y is an approximation to rcip(x); comparing means for comparing the computed error, 1-x×y, to 1-x×(y+2 -53 ); and means for selecting a result with less error.
Claim 15
Dependent Claim 32 words
An FPU according to claim 13 wherein if the compared results in the comparing means have equal errors, then said means for selecting selects a result with a low bit of 0.
Claim 16
Dependent Claim 130 words
An FPU according to claim 1 wherein a square root (SQRT(x)) is being computed and the multiply accumulate function generates n extra bits more than is allotted to the mantissa when computing the polynomial approximation of the square root function, further comprising: detecting means for detecting if a bit pattern in the n extra bits is 11111 . . . (i.e., n 1s), this bit pattern signifying that the mantissa is potentially 1 bit more than required and should be compared to a result with an incremented mantissa; error computation means for computing an error, x-y 2 , where y is the approximation to sqrt(x); comparing means for comparing the computed error, x-y 2 , to x-(y+2 -52 ) 2 ; and means for selecting a result with less error.
Claim 17
Dependent Claim 32 words
An FPU according to claim 15 wherein if the compared results in the comparing means have equal errors, then said means for selecting selects a result with a low bit of 0.
Claim 18
Dependent Claim 121 words
An FPU according to claim 1 wherein a reciprocal (RCIP(x)) is being computed and the multiply accumulate function generates n extra bits more than is allotted to the mantissa when computing the polynomial approximation of the reciprocal function, further comprising: detecting means for detecting a bit pattern in the n extra bits of 00000 . . . (i.e., n 0s), this bit pattern signifying that the mantissa is potentially 1 bit more than required and should be compared to a result with a decremented mantissa; error computation means for computing an error, 1-x×y, where y is an approximation to rcip(x); comparing means for comparing the computed error, 1-x×y, to 1-x×(y-2 -53 ); and means for selecting a result with less error.
Claim 19
Dependent Claim 32 words
An FPU according to claim 17 wherein if the compared results in the comparing means have equal errors, then said means for selecting selects a result with a low bit of 0.
Claim 20
Dependent Claim 130 words
An FPU according to claim 1 wherein a square root (SQRT(x)) is being computed and the multiply accumulate function generates n extra bits more than is allotted to the mantissa when computing the polynomial approximation of the square root function, further comprising: detecting means for detecting if a bit pattern in the n extra bits is 00000 . . . (i.e., n 0s), this bit pattern signifying that the mantissa is potentially 1 bit more than required and should be compared to a result with a decremented mantissa; error computation means for computing an error, x-y 2 , where y is the approximation to sqrt(x); comparing means for comparing the computed error, x-y 2 , to x-(y-2 -52 ) 2 ; and means for selecting a result with less error.
Claim 21
Dependent Claim 32 words
An FPU according to claim 19 wherein if the compared results in the comparing means have equal errors, then said means for selecting selects a result with a low bit of 0.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-04-18 1997-10-18 1998-04-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-04-18 2001-10-18 2002-04-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-04-18 2005-10-18 2006-04-19 $7700.00 Window Closed / Lapsed

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