Digital polynomial function generator

Claim 1

Apparatus for obtaining a digital value of a function expressed by: w = a.sub.0 + a.sub.1 x + a.sub.2 x.sup.2 + . . . + a.sub.n x.sup.n where w is the function the value of which is to be obtained, a 0 , a 1 , a 2 , . . . , a n are constants, x is the independent variable, n is an integer and n≧2, comprising: a shift register means composed of blocks B0, B1, B2, . . . , Bn having equal bit lengths of storage and arranged in the order of B0, B1, B2, . . . , Bn and having first and second output terminals and an input terminal, means for loading each block of said shift register means with respective specific numerical value determined by the constants a 0 , a 1 , a 2 , . . . , a n , control means for supplying shift pulses to said shift register blocks to shift the contents of said blocks of said shift register means, means for reading out serially the contents of said shift register means in response to said shift pulses in the order of B0, B1, B2, . . . , Bn from said first output terminal, and, simultaneously, in the order of B1, B2, . . . , Bn from said second output terminal of said shift register means, a serial full adder means having two input terminals and one output terminal, means for supplying said read out digits from said first output terminal of said shift register means to one of the input terminals of said full adder means, means for supplying said read out digits from said second output terminal of said shift register means to the other of the input terminals of said full adder means, means for supplying the digits from said output terminal of said full adder means to said input terminal of said shift register means to be rewritten therein, said control means, for performing one cycle of cascade additions, supplying a number of shift pulses selected in number in accordance with the number of storage bits of said blocks of said shift register means to shift the bits through all blocks of said shift register, said one cycle of cascade additions being divided into n+1 equal time intervals during each of which the bits of each block are shifted to the next successive block in said shift register means, means for interrupting the digits read out from said second output terminal of said shift register means to be supplied to the other input terminal of said full adder means during the last one of said time intervals, and said control means performing a number of cycles of cascade additions corresponding to the value of the independent variable x, thereby to obtain the value of the function w in the block B0 of said shift register means.