Open bit line memory devices and operational method

Claim 2

An open bit line memory device comprising: a plurality of memory cells arranged in an open bit line configuration, at least some of said memory cells being interconnected by a bit line, said bit line performing selection of said interconnected memory cells; a signal detection unit coupled to said bit line for sensing a developing signal thereon during a predefined bit line signal development interval, said signal detection unit including means for setting to one of two logical states during a setting interval, said setting interval being subsequent to said predefined bit line signal development interval; and means for electrically isolating said bit line from said signal detection unit for at least a portion of said setting interval so that any signal variations on said bit line are isolated from said detection unit.

Claim 3

The open bit line memory device of claim 1, wherein said electrical isolating means isolates said signal detection unit from said bit line for the entire length of said setting interval.

Claim 4

The open bit line memory device of claim 1, wherein said plurality of memory cells comprises an array of memory cells, and wherein a plurality of signal detection units are provided, each signal detection unit comprising a sense amplifier unit, said sense amplifier units being arranged in at least one sense amplifier bank, and each of said sense amplifier units having at least one bit line coupled thereto for sensing a developing signal thereon during said predefined bit line signal development interval.

Claim 5

The open bit line memory device of claim 3, wherein said cells of said memory array are arranged in rows and columns, said plurality of bit lines performing column selection of memory cells, and wherein said device further comprises a plurality of periodically spaced word lines for performing row selection of memory cells.

Claim 6

The open bit line memory device of claim 4, wherein said memory array is disposed within an array well defined within a supporting substrate.

Claim 7

The open bit line memory device of claim 1, wherein said electrical isolating means includes a bit line isolation device disposed between said signal detection unit and said bit line, said bit line isolation device being responsive to a predefined bit line isolation control signal.

Claim 8

The open bit line memory device of claim 1, further comprising a predefined reference voltage signal coupled to an input of said signal detection unit, said predefined reference voltage signal being associated with said bit line, and said isolation means including means for isolating said bit line and said reference voltage signal from said signal detection unit during at least a portion of said setting interval.

Claim 9

The open bit line memory device of claim 7, further comprising equalization means for selectively equalizing a signal on said bit line with said predefined reference voltage signal.

Claim 10

The open bit line memory device of claim 7, wherein said electrical isolation means includes a first switched gate isolation device coupled between said bit line and said signal detection unit, said first switched gate isolation device being controlled by a predefined bit line isolation control signal, and a second switched gate isolation device disposed between a source of said predefined reference voltage signal and said signal detection unit, said second switched gate isolation device being controlled by a predefined reference isolation control signal.

Claim 11

The open bit line memory device of claim 1, further comprising at least one data line coupled to said signal detection signal for receiving a set signal therefrom, said set signal comprising one of said two logical states.

Claim 12

The open bit line memory device of claim 10, wherein said signal detection unit comprises a sense amplifier unit, said sense amplifier unit including at least one cross-coupled pairing of transistors.

Claim 13

A dynamic random access memory device comprising: a plurality of memory cells arranged in an open bit line configuration, at least some of said memory cells being interconnected by a bit line, said bit line for performing selection of said interconnected memory cells; means for selecting a particular one of said interconnected memory cells for reading; a reference voltage line associated with said one bit line, said reference voltage line providing a reference voltage signal, a sense amplifier coupled to said one bit line for sensing a developing signal from said selected one of said plurality of interconnected memory cells during a predefined bit line signal development period, said sense amplifier also being coupled to said reference voltage line for receiving said reference voltage signal, said sense amplifier including means for setting to one of two logic states based upon a determined differential between a sensed signal on said bit line and said reference voltage signal during a predefined setting period; and means for electrically isolating said bit line and said associated reference voltage line from said sense amplifier for at least a portion of said predefined setting period so that any signal variations on said bit line or said associated reference voltage line are isolated from said sense amplifier.

Claim 14

A dynamic random access memory device comprising: a plurality of memory cells arranged in an open bit line configuration, at least some of said memory cells being interconnected by a bit line, said bit line for performing selection of said interconnected memory cells; means for selecting a particular one of said interconnected memory cells for reading; a reference voltage line associated with said one bit line, said reference voltage line providing a reference voltage signal, a sense amplifier coupled to said one bit line for sensing a developing signal from said selected one of said plurality of interconnected memory cells during a predefined bit line signal development period, said sense amplifier also being coupled to said reference voltage line for receiving said reference voltage signal, said sense amplifier including means for setting to one of two logic states based upon a determined differential between a sensed signal on said bit line and said reference voltage signal during a predefined setting period; and means for electrically isolating said bit line and said associated reference voltage line from said sense amplifier for at least a portion of said predefined setting period so that any signal variations on said bit line or said associated reference voltage line are isolated from said sense amplifier.

Claim 15

The dynamic random access memory device of claim 12, wherein said electrical isolating means isolates said sense amplifier from said bit line and said reference voltage line for the entire amplifier setting interval.

Claim 16

The dynamic random access memory device of claim 12, wherein said plurality of memory cells comprise a memory array, said memory array being disposed within an array well within a supporting substrate.

Claim 17

The dynamic random access memory device of claim 12, wherein said sense amplifier comprises a bank of sense amplifier units, and further wherein a plurality of bit lines are provided, each of said bit lines interconnecting at least some of said memory cells, and wherein each of said sense amplifier units couples to a unique one of said plurality of bit lines.

Claim 18

The dynamic random access memory device of claim 12, wherein said electrical isolating means includes a bit line isolation transistor disposed between said sense amplifier and said bit line, said bit line isolation transistor being responsive to a predefined bit line isolation control signal, and wherein said isolating means further includes a reference voltage line isolation transistor disposed between said sense amplifier and a source of said reference voltage signal, said reference voltage line isolation transistor being responsive to a pre-defined reference isolation control signal.

Claim 19

The dynamic random access memory device of claim 12, further comprising equalization means for equalizing a signal on said bit line with said pre-defined reference voltage signal for a predefined equalization charging interval before said predefined bit line signal development interval.

Claim 20

The dynamic random access memory device of claim 12, further comprising at least one data line coupled to said sense amplifier for reading a set signal therefrom, said amplifier set signal comprising one of said two logical states.

Claim 21

A memory cell reading method for an open bit line configured memory device having a plurality of memory cells arranged in rows and columns and a signal sensing device associated with said memory cells, said device further including a plurality of periodically spaced bit lines for performing column selection of memory cells and a plurality of periodically spaced word lines for performing row selection of memory cells, said cell reading method comprising the steps of: (a) allowing a signal to develop on one of said plurality of bit lines representative of the state of a selected one of a plurality of memory cells interconnected by said bit line; (b) using said sensing device to read the signal on said one bit line of step (a) during a predefined bit line signal development period; (c) isolating said one bit line from said sensing device; and (d) at least partially simultaneous with said step (c), setting said sensing device to one of two logical states based upon said signal developed in said step (a) on said one bit line, said isolating step (c) allowing said sensing device to at least partially set independent of continuing signal variations on said one bit line.

Claim 22

A memory cell reading method for an open bit line configured memory device having a plurality of memory cells arranged in rows and columns and a signal sensing device associated with said memory cells, said device further including a plurality of periodically spaced bit lines for performing column selection of memory cells and a plurality of periodically spaced word lines for performing row selection of memory cells, said cell reading method comprising the steps of: (a) allowing a signal to develop on one of said plurality of bit lines representative of the state of a selected one of a plurality of memory cells interconnected by said bit line; (b) using said sensing device to read the signal on said one bit line of step (a) during a predefined bit line signal development period; (c) isolating said one bit line from said sensing device; and (d) at least partially simultaneous with said step (c), setting said sensing device to one of two logical states based upon said signal developed in said step (a) on said one bit line, said isolating step (c) allowing said sensing device to at least partially set independent of continuing signal variations on said one bit line.

Claim 23

The memory cell reading method of claim 19, wherein said step (d) includes setting said sensing device to said one of two logical states simultaneous with said isolating step (c).

Claim 24

The memory cell reading method of claim 19, further comprising the step of providing a reference voltage signal to said sensing device, said reference voltage signal being associated with said one bit line, said sensing device setting of step (d) including determining a differential between the signal read on said one bit line and said reference voltage signal.

Claim 25

The memory cell reading method of claim 21, wherein said isolating step (c) further includes isolating said reference voltage signal from said sensing device.

Claim 26

The memory cell reading method of claim 19, further comprising the step of providing a reference voltage signal, said reference voltage signal being associated with said one bit line, and wherein said memory cell reading method further includes equalizing a signal on said one bit line with said reference voltage signal prior to said bit line signal development of step (a), and wherein said allowing step (a) includes discontinuing said equalizing of the signal on said one bit line and said reference voltage signal.

Claim 27

The memory cell reading method of claim 19, further comprising the step of selecting said one memory cell to be read, said memory cell selecting step employing a corresponding one of said plurality of periodically spaced word lines.

Claim 28

The memory cell reading method of claim 19, further comprising the steps of discontinuing said isolating of step (c) subsequent said setting of said sensing device, and rewriting said selected one of said plurality of memory cells with a value corresponding to the signal read therefrom.