Patent US5301155A successfully refreshed from Google Patents.
US5301155A
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Multiblock semiconduction storage device including simultaneous operation of a plurality of block defect determination circuits
Assignee: Mitsubishi Electric Corp
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Filing: 1991-03-18
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Granted: 1994-04-05
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Expires: 2011-03-18
Abstract
Abstract A semiconductor storage device including a plurality of blocks each having an array of memory cells includes an exclusive OR circuit provided in each of the plurality of blocks for making a determination as to whether data written in memory cells in the blocks are normally read. Exclusive OR circuits of a plurality of memory cell array blocks are connected to an OR circuit. With an output signal from the OR circuit, a determination is made as to whether a plurality of memory cell array blocks are normal or not. Since test data from a plurality of memory cell array blocks are simultaneously examined by an OR circuit, a test time for the semiconductor storage device can be reduced.
Inventors
- 👤 Tomohisa Wada
- 👤 Shuji Murakami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:41
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/38; G11C29/40; G11C29/18; G11C29/26; G11C29/28
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
100 words
A semiconductor storage device, comprising: a plurality of blocks each including an array of memory cells; means for writing identical data into a plurality of memory cells in each of at least two blocks; a plurality of memory cell operation determination means each provided corresponding to a block for simultaneously reading data from the plurality of memory cells in each block in which said identical data was written and making a determination as to whether the read data are all identical; and simultaneous determination means for simultaneously operating at least two of said plurality of memory cell operation determination means.
Claim 2
Dependent Claim
100 words
A semiconductor storage device, comprising: a plurality of blocks each including an array of memory cells; means for writing identical data into a plurality of memory cells in each of at least two blocks; a plurality of memory cell operation determination means each provided corresponding to a block for simultaneously reading data from the plurality of memory cells in each block in which said identical data was written and making a determination as to whether the read data are all identical; and simultaneous determination means for simultaneously operating at least two of said plurality of memory cell operation determination means.
Claim 3
Dependent Claim
53 words
The semiconductor storage device according to claim 1, wherein said memory cell operation determination means comprises data writing means for writing predetermined data into said memory cells and data reading means for reading said written data, and makes a determination as to whether said written data and read data are identical or not.
Claim 4
Dependent Claim
17 words
The semiconductor storage device according to claim 2, wherein said operation determination means comprises a logic circuit.
Claim 5
Dependent Claim
18 words
The semiconductor storage device according to claim 3, wherein said logic circuit comprises an exclusive logic NOR circuit.
Claim 6
Dependent Claim
35 words
The semiconductor storage device according to claim 1, wherein said simultaneous determination means makes a determination about said plurality of blocks on the basis of a determination result of each of said operation determination means.
Claim 7
Dependent Claim
17 words
The semiconductor storage device according to claim 5, wherein said simultaneous determination means comprises a logic circuit.
Claim 8
Dependent Claim
29 words
The semiconductor storage device according to claim 6, wherein said logic circuit comprises an electric field effect element operating in response to an output of said each determination means.
Claim 9
Independent Claim
77 words
A method of making a determination whether a semiconductor storage device, including a plurality of blocks each having an array of memory cells, is defective, comprising the steps of: writing identical data into a plurality of memory cells in at least two blocks; and concurrently, for said at least two blocks, simultaneously reading the data from the plurality of memory cells in which said identical data was written and determining whether the read data are all identical.
Claim 10
Independent Claim
77 words
A method of making a determination whether a semiconductor storage device, including a plurality of blocks each having an array of memory cells, is defective, comprising the steps of: writing identical data into a plurality of memory cells in at least two blocks; and concurrently, for said at least two blocks, simultaneously reading the data from the plurality of memory cells in which said identical data was written and determining whether the read data are all identical.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-04 | 1997-10-04 | 1998-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-04 | 2001-10-04 | 2002-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-04 | 2005-10-04 | 2006-04-05 | $7700.00 | Window Closed / Lapsed |