Semiconductor wafer with improved step coverage along scribe lines

Claim 2

A semiconductor wafer partitioned into a multiplicity of chip areas defined by a grid-like array of scribe lines inscribed into the surface of the wafer, wherein each scribe line is longitudinally bounded by respective field oxide layers formed in the surface of the wafer, to thereby define a scribe line region between adjacent chip areas, including; a multiplicity of integrated circuits formed in a corresponding multiplicity of the chip areas, respectively, each of said integrated circuits including a patterned, multilayer structure having a peripheral edge portion which extends into a respective one of the scribe line regions; wherein said peripheral edge portion of each said multilayer structure has a multi-tiered cross-sectional profile; wherein each said multilayer structure is comprised of a plurality of individual layers each having a peripheral edge portion which extends into said respective one of the scribe line regions, wherein the length of said peripheral edge portion of each said individual layer is different; and, wherein, for each said multilayer structure, the length of said peripheral edge portion of each said individual layer is greater than that of the other ones of said individual layers disposed thereabove.

Claim 3

The wafer as set forth in claim 1, wherein, for each said multilayer structure, the difference in the length of said peripheral edge portion of successive ones of said individual layers is constant.

Claim 4

A semiconductor wafer partitioned into a multiplicity of chip areas defined by a grid-like array of scribe lines inscribed into the surface of the wafer, wherein each scribe line is longitudinally bounded by respective field oxide layers formed in the surface of the wafer, to thereby define a scribe line region between adjacent chip areas, including: a multiplicity of integrated circuits formed in a corresponding multiplicity of the chip areas, respectively, each of said integrated circuits including a patterned, multilayer structure having a peripheral edge portion which extends into a respective one of the scribe line regions; wherein said peripheral edge portion of each said multilayer structure has a multi-tiered cross-sectional profile; wherein each said multilayer structure is comprised of a plurality of individual layers each having a peripheral edge portion which extends into said respective one of the scribe line regions, wherein the length of said peripheral edge portion of each said individual layer is different; and, wherein, for each said multilayer structure, the length of said peripheral edge portion of each said individual layer is less than that of the other ones of said individual layers disposed thereabove.

Claim 5

A semiconductor wafer partitioned into a multiplicity of chip areas defined by a grid-like array of scribe lines inscribed into the surface of the wafer, wherein each scribe line is longitudinally bounded by respective field oxide layers formed in the surface of the wafer, to thereby define a scribe line region between adjacent chip areas, including: a multiplicity of integrated circuits formed in a corresponding multiplicity of the chip areas, respectively, each of said integrated circuits including a patterned, multilayer structure having a peripheral edge portion which extends into a respective one of the scribe line regions; wherein said peripheral edge portion of each said multilayer structure has a multi-tiered cross-sectional profile; wherein each said multilayer structure is comprised of a plurality of individual layers each having a peripheral edge portion which extends into said respective one of the scribe line regions, wherein the length of said peripheral edge portion of each said individual layer is different; and, wherein, for each said multilayer structure, the length of said peripheral edge portion of each said individual layer is less than that of the other ones of said individual layers disposed thereabove.

Claim 6

The wafer as set forth in claim 3, wherein, for each said multilayer structure, said peripheral edge portion of each said individual layer completely overlies said peripheral edge portion of the other ones of said individual layers disposed therebeneath.

Claim 7

The wafer as set forth in claim 4, wherein, for each said multilayer structure, each said individual layer has a distal foot portion disposed on the surface of the wafer, wherein said distal foot portion of each said individual layer extends beyond said distal foot portion of the other ones of said individual layers disposed therebeneath.

Claim 8

The wafer as set forth in claim 5, wherein, for each said multilayer structure, the difference in the length of said peripheral edge portion of successive ones of said individual layers is constant.

Claim 9

A semiconductor wafer partitioned into a multiplicity of chip areas defined by a grid-like array of scribe lines inscribed into the surface of the wafer, wherein each scribe line is longitudinally bounded by respective field oxide layers formed in the surface of the wafer, to thereby define a scribe line region between adjacent chip areas, including: a multiplicity of integrated circuits formed in a corresponding multiplicity of the chip areas, respectively, each of said integrated circuits including a patterned, multilayer structure having a peripheral edge portion which extends into a respective one of the scribe line regions; wherein said peripheral edge portion of each said multilayer structure has a multi-tiered cross-sectional profile; wherein each said multilayer structure is comprised of a plurality of individual layers each having a peripheral edge portion which extends into said respective one of the scribe line regions, wherein the length of said peripheral edge portion of each said individual layer is different; and, wherein, for each said multilayer structure: said plurality of individual layers include first alternate ones comprised of successive, alternate ones of said individual layers, beginning with the bottommost individual layer, and, second alternate ones comprised of successive, alternate ones of said individual layers, beginning with the next-to-bottommost individual layer; the length of said peripheral edge portion of each said individual layer of said first alternate ones is greater than that of the other ones of said individual layers of said first alternate ones disposed thereabove; and, the length of said peripheral edge portion of each said individual layer of said second alternate ones is less than that of the other ones of said individual layers of said second alternate ones disposed thereabove.

Claim 10

A semiconductor wafer partitioned into a multiplicity of chip areas defined by a grid-like array of scribe lines inscribed into the surface of the wafer, wherein each scribe line is longitudinally bounded by respective field oxide layers formed in the surface of the wafer, to thereby define a scribe line region between adjacent chip areas, including: a multiplicity of integrated circuits formed in a corresponding multiplicity of the chip areas, respectively, each of said integrated circuits including a patterned, multilayer structure having a peripheral edge portion which extends into a respective one of the scribe line regions; wherein said peripheral edge portion of each said multilayer structure has a multi-tiered cross-sectional profile; wherein each said multilayer structure is comprised of a plurality of individual layers each having a peripheral edge portion which extends into said respective one of the scribe line regions, wherein the length of said peripheral edge portion of each said individual layer is different; and, wherein, for each said multilayer structure: said plurality of individual layers include first alternate ones comprised of successive, alternate ones of said individual layers, beginning with the bottommost individual layer, and, second alternate ones comprised of successive, alternate ones of said individual layers, beginning with the next-to-bottommost individual layer; the length of said peripheral edge portion of each said individual layer of said first alternate ones is greater than that of the other ones of said individual layers of said first alternate ones disposed thereabove; and, the length of said peripheral edge portion of each said individual layer of said second alternate ones is less than that of the other ones of said individual layers of said second alternate ones disposed thereabove.

Claim 11

The wafer as set forth in claim 7, wherein, for each said multilayer structure, each said individual layer of said second alternate ones has a distal foot portion disposed on the surface of the wafer, wherein said distal foot portion of each said individual layer of said second alternate ones extends beyond said distal foot portion of the other ones of said individual layers of said second alternate ones disposed therebeneath.

Claim 12

The wafer as set forth in claim 8, wherein, for each said multilayer structure, the difference in the length of said peripheral edge portion of successive ones of said individual layers of said second alternate ones is constant.

Claim 13

The wafer as set forth in claim 9, wherein, for each said multilayer structure, the difference in the length of said peripheral edge portion of successive ones of said individual layers of said first alternate ones is constant.

Claim 14

A semiconductor wafer partitioned into a multiplicity of chip areas defined by a grid-like array of scribe lines inscribed into the surface of the wafer, wherein each scribe line is longitudinally bounded by respective field oxide layers formed in the surface of the wafer, to thereby define a scribe line region between adjacent chip areas, including: a multiplicity of integrated circuits formed in a corresponding multiplicity of the chip areas, respectively, each of said integrated circuits including a patterned, multilayer structure having a peripheral edge portion which extends into a respective one of the scribe line regions; wherein said peripheral edge portion of each said multilayer structure has a multi-tiered cross-sectional profile; wherein each said multilayer structure is comprised of a plurality of individual layers each having a peripheral edge portion which extends into said respective one of the scribe line regions, wherein the length of said peripheral edge portion of each said individual layer is different; and, wherein, for each said multilayer structure: said plurality of individual layers include first alternate ones comprised of successive, alternate ones of said individual layers, beginning with the bottommost individual layer, and, second alternate ones comprised of successive, alternate ones of said individual layers, beginning with the next-to-bottommost individual layer; the length of said peripheral edge portion of each said individual layer of said first alternate ones is less than that of the other ones of said individual layers of said first alternate ones disposed thereabove; and, the length of said peripheral edge portion of each said individual layer of said second alternate ones is greater than that of the other ones of said individual layers of said second alternate ones disposed thereabove.

Claim 15

A semiconductor wafer partitioned into a multiplicity of chip areas defined by a grid-like array of scribe lines inscribed into the surface of the wafer, wherein each scribe line is longitudinally bounded by respective field oxide layers formed in the surface of the wafer, to thereby define a scribe line region between adjacent chip areas, including: a multiplicity of integrated circuits formed in a corresponding multiplicity of the chip areas, respectively, each of said integrated circuits including a patterned, multilayer structure having a peripheral edge portion which extends into a respective one of the scribe line regions; wherein said peripheral edge portion of each said multilayer structure has a multi-tiered cross-sectional profile; wherein each said multilayer structure is comprised of a plurality of individual layers each having a peripheral edge portion which extends into said respective one of the scribe line regions, wherein the length of said peripheral edge portion of each said individual layer is different; and, wherein, for each said multilayer structure: said plurality of individual layers include first alternate ones comprised of successive, alternate ones of said individual layers, beginning with the bottommost individual layer, and, second alternate ones comprised of successive, alternate ones of said individual layers, beginning with the next-to-bottommost individual layer; the length of said peripheral edge portion of each said individual layer of said first alternate ones is less than that of the other ones of said individual layers of said first alternate ones disposed thereabove; and, the length of said peripheral edge portion of each said individual layer of said second alternate ones is greater than that of the other ones of said individual layers of said second alternate ones disposed thereabove.

Claim 16

The wafer as set forth in claim 11, wherein, for each said multilayer structure, each said individual layer of said first alternate ones has a distal foot portion disposed on the surface of the wafer, wherein said distal foot portion of each said individual layer of said first alternate ones extends beyond said distal foot portion of the other ones of said individual layers of said first alternate ones disposed therebeneath.

Claim 17

The wafer as set forth in claim 12, wherein, for each said multilayer structure, the difference in the length of said peripheral edge portion of successive ones of said individual layers of said first alternate ones is constant.

Claim 18

The wafer as set forth in claim 13, wherein, for each said multilayer structure, the difference in the length of said peripheral edge portion of successive ones of said individual layers of said second alternate ones is constant.