US5300460A — UHF/VHF plasma for use in forming integrated circ…

Claim 1

Independent Claim 148 words

A low presure plasma-assisted RIE process for anisotropically etching silicon oxide in the fabrication of integrated circuit devices on semiconductor wafers characterized by the generation, in a vacuum etching chamber, of a plasma using a power source having a frequency range of from about 100 MHz up to about 250 MHz to provide a sheath voltage low enough to avoid risk of damage to devices on said wafer during said etching and maintained at a power density level ranging from about 30 to about 76 watts/inch 2 of wafer area, while flowing one or more fluorine-containing gases and one or more carbon-containing gases into said vacuum etching chamber containing an anode and a wafer mounted on a cathode and maintained at a pressure within a range of from about 2 to about 500 milliTorr to provide a silicon oxide etch rate of from about 0.3 to 0.75 microns/minute.

Claim 2

Dependent Claim 148 words

A low presure plasma-assisted RIE process for anisotropically etching silicon oxide in the fabrication of integrated circuit devices on semiconductor wafers characterized by the generation, in a vacuum etching chamber, of a plasma using a power source having a frequency range of from about 100 MHz up to about 250 MHz to provide a sheath voltage low enough to avoid risk of damage to devices on said wafer during said etching and maintained at a power density level ranging from about 30 to about 76 watts/inch 2 of wafer area, while flowing one or more fluorine-containing gases and one or more carbon-containing gases into said vacuum etching chamber containing an anode and a wafer mounted on a cathode and maintained at a pressure within a range of from about 2 to about 500 milliTorr to provide a silicon oxide etch rate of from about 0.3 to 0.75 microns/minute.

Claim 3

Dependent Claim 34 words

The process of claim 1 wherein said anode and cathode electrodes have a ratio of anode to cathode area of at least about 2:1 and an electrode spacing of about 5 cm. or more.

Claim 4

Dependent Claim 24 words

The process of claim 1 wherein said anode and cathode electrodes have an electrode spacing ranging from about 5 cm. to about 30 cm.

Claim 5

Dependent Claim 24 words

The process of claim 1 wherein said power source is operated within a frequency range of from about 150 MHz to about 200 MHz.

Claim 6

Dependent Claim 19 words

The process of claim 2 wherein said pressure in said chamber ranges from about 20 to about 200 milliTorr.

Claim 7

Dependent Claim 21 words

The process of claim 2 wherein said power density ranges from about 45 to about 56 watts/in 2 of wafer area.

Claim 8

Dependent Claim 28 words

The process of claim 2 which further comprises flowing an optional source of hydrogen and an optional inert gas through said chamber while said plasa is ignited therein.

Claim 9

Dependent Claim 77 words

The process of claim 7 wherein said RIE process comprises a selective process for etching silicon oxide in preference to polysilicon or photoresist wherein the atomic ratio of carbon to fluorine ranges from about 0.1:1 to about 2:1 and the atomic ratio of hydrogen present to fluorine ranges from about 0.1:1 to 0.5:1 to obtain a ratio of silicon oxide etch (thickness) rate to polysilicon or photoresist etch (thickness) rate of from about 2:1 to over 30:1.

Claim 10

Dependent Claim 166 words

A plasma-assisted high pressure process for etching silicon oxide in the fabrication of integrated circuit devices on semiconductorb wafers characterized by the generation, in a vacuum etching chamber, of a plasma using one or more power sources having a frequency range of from about 100 MHz up to about 200 MHz to provide a sheath voltage low enough to avoid risk of damage to devices on said wafer during said etching and maintained at a power density level ranging from about 30 to about 50 watts/inch 2 of wafer area, while flowing one or more fluorine-containing gases and one or more carbon-containing gases into said vacuum etching chamber containing an anode and a wafer mounted on a cathode spaced from said anode a distance ranging from about 0.2 to less than about 5 cm., said vacuum chamber maintained at a pressure within a range of over 500 milliTorr to about 50 Torr to provide a silicon oxide removal rate of about 0.2 to about 1 micron/minute.

Claim 11

Dependent Claim 166 words

A plasma-assisted high pressure process for etching silicon oxide in the fabrication of integrated circuit devices on semiconductorb wafers characterized by the generation, in a vacuum etching chamber, of a plasma using one or more power sources having a frequency range of from about 100 MHz up to about 200 MHz to provide a sheath voltage low enough to avoid risk of damage to devices on said wafer during said etching and maintained at a power density level ranging from about 30 to about 50 watts/inch 2 of wafer area, while flowing one or more fluorine-containing gases and one or more carbon-containing gases into said vacuum etching chamber containing an anode and a wafer mounted on a cathode spaced from said anode a distance ranging from about 0.2 to less than about 5 cm., said vacuum chamber maintained at a pressure within a range of over 500 milliTorr to about 50 Torr to provide a silicon oxide removal rate of about 0.2 to about 1 micron/minute.

Claim 12

Dependent Claim 27 words

The process of claim 9 wherein said high pressure plasma etching process is operated within a pressure range of from about 1 Torr to about 20 Torr.

Claim 13

Dependent Claim 25 words

The process of claim 6 which further comprises flowing an optional source of hydrogen and an optional inert gas through said chamber during said etch.

Claim 14

Dependent Claim 82 words

The process of claim 11 wherein said high pressure plasma silicon oxide etch process comprises a selective process for etching silicon oxide in preference to polysilicon or photoresist wherein the atomic ratio of carbon to fluorine ranges from about 0.1:1 to about 2:1 and the atomic ratio of hydrogen present to fluorine ranges from about 0.1:1 to 0.5:1 to obtain a ratio of silicone oxide etch (thickness) rate to polysilicon or photoresist etch (thickness) rate of from about 2:1 to over 30:1.

Claim 15

Dependent Claim 163 words

A plasma-assisted low pressure CVD process for depositing materials selected from the group consisting of silicon oxide and silicon nitride used in the fabrication of integrated circuit devices on semiconductor wafers characterized by the generation, in a vacuum deposition chamber of a plasma using one or more power sources having a frequency range of from about 100 MHz up to about 250 MHz to provide a sheath voltage low enough to avoid risk of damage to devices on said wafer during said deposition process and maintained at a power density level ranging from about 30 to about 76 watts/inch 2 of wafer area in a vacuum deposition chamber containing an anode and a wafer mounted on a cathode spaced from said anode a distance of from about 5 to about 30 cm., said vacuum chamber maintained at a pressure within a range of from about 2 to about 500 milliTorr to provide a deposition rate of from about 0.1 to about 1.5 microns/minute.

Claim 16

Dependent Claim 163 words

A plasma-assisted low pressure CVD process for depositing materials selected from the group consisting of silicon oxide and silicon nitride used in the fabrication of integrated circuit devices on semiconductor wafers characterized by the generation, in a vacuum deposition chamber of a plasma using one or more power sources having a frequency range of from about 100 MHz up to about 250 MHz to provide a sheath voltage low enough to avoid risk of damage to devices on said wafer during said deposition process and maintained at a power density level ranging from about 30 to about 76 watts/inch 2 of wafer area in a vacuum deposition chamber containing an anode and a wafer mounted on a cathode spaced from said anode a distance of from about 5 to about 30 cm., said vacuum chamber maintained at a pressure within a range of from about 2 to about 500 milliTorr to provide a deposition rate of from about 0.1 to about 1.5 microns/minute.

Claim 17

Dependent Claim 19 words

The process of claim 13 wherein said pressure in said chamber ranges from about 20 to about 200 milliTorr.

Claim 18

Dependent Claim 21 words

The process of claim 14 wherein said power density ranges from about 45 to about 56 watts/in 2 of wafer area.

Claim 19

Dependent Claim 35 words

The process of claim 15 which further comprises flowing one or more sources of silicon, one or more sources of oxygen, and an optional inert gas through said chamber while said plasme is ignited therein.

Claim 20

Dependent Claim 40 words

The process of claim 13 which further comprises flowing one or more sources of silicon, one or more sources of nitrogen, an optional source of hydrogen, and an optional inert gas through said chamber while said plasma is ignited there.

Claim 21

Dependent Claim 164 words

A plasma-assisted high pressure CVD conformal isotropic process for depositing materials selected from the group consisting of silicon oxide and silicon nitride used in the fabrication of integrated circuit devices on semiconductor wafers characterized by the generation, in a vacuum deposition chamber of a plasma using one or more power sources having a frequency range of from about 150 MHz up to about 800 MHz to provide a sheath voltage low enough to avoid risk of damage to devices on said wafer during said deposition process and maintained at a power density level ranging from about 10 to about 38 watts/inch 2 of wafer area in a vacuum etching chamber containing an anode and a wafer mounted ona cathode spaced from said anode a distance of from about 0.2 to about 5 cm., said vacuum chamber maintained at a pressure within a range of over 500 milliTorr to about 50 Torr to provide a deposition rate of from about 0.5 to about 1.0 microns/minute.

Claim 22

Dependent Claim 164 words

A plasma-assisted high pressure CVD conformal isotropic process for depositing materials selected from the group consisting of silicon oxide and silicon nitride used in the fabrication of integrated circuit devices on semiconductor wafers characterized by the generation, in a vacuum deposition chamber of a plasma using one or more power sources having a frequency range of from about 150 MHz up to about 800 MHz to provide a sheath voltage low enough to avoid risk of damage to devices on said wafer during said deposition process and maintained at a power density level ranging from about 10 to about 38 watts/inch 2 of wafer area in a vacuum etching chamber containing an anode and a wafer mounted ona cathode spaced from said anode a distance of from about 0.2 to about 5 cm., said vacuum chamber maintained at a pressure within a range of over 500 milliTorr to about 50 Torr to provide a deposition rate of from about 0.5 to about 1.0 microns/minute.

Claim 23

Dependent Claim 23 words

The process of claim 18 which further comprises maintaining a pressure in said chamber ranging from about 1 Torr to about 20 Torr.

Claim 24

Dependent Claim 31 words

The process of claim 9 wherein said process further comprises flowing one or more sources of silicon, one or more sources of oxygen, and an optional inert gas through the chamber.

Claim 25

Dependent Claim 36 words

The process of claim 19 wherein said process further comprises flowing one or more sources of silicon, one or more sources of nitrogen, an optional source of hydrogen, and an optional inert gas through the chamber.

Claim 26

Dependent Claim 164 words

A low pressure plasma-assisted RIE process for anisotropically etching a material selected from the group consisting of aluminum and polysilicon in the fabrication of integrated circuit devices on semiconductor wafers characterized by the generation, in a vacuum etching chamber, of a plasma using a power source having a frequency range of from about 150 MHz up to about 600 MHz to provide a sheath voltage low enough to avoid risk of damage to devices on said wafer during said etching and maintained at a power density level ranging from about 20 to about 40 watts/inch 2 of wafer area, while flowing a mixture of one or more chlorine-containing gases and one or more inert gases into said vacuum etching chamber containing an anode and a wafer mounted on a cathode and maintained at a pressure within a range of from about 2 to about 500 milliTorr to provide an aluminum or polysilicon etch rate of froma bout 0.2 to about 1 microns per minute.

Claim 27

Dependent Claim 164 words

A low pressure plasma-assisted RIE process for anisotropically etching a material selected from the group consisting of aluminum and polysilicon in the fabrication of integrated circuit devices on semiconductor wafers characterized by the generation, in a vacuum etching chamber, of a plasma using a power source having a frequency range of from about 150 MHz up to about 600 MHz to provide a sheath voltage low enough to avoid risk of damage to devices on said wafer during said etching and maintained at a power density level ranging from about 20 to about 40 watts/inch 2 of wafer area, while flowing a mixture of one or more chlorine-containing gases and one or more inert gases into said vacuum etching chamber containing an anode and a wafer mounted on a cathode and maintained at a pressure within a range of from about 2 to about 500 milliTorr to provide an aluminum or polysilicon etch rate of froma bout 0.2 to about 1 microns per minute.

Claim 28

Dependent Claim 19 words

The process of claim 22 wherein said pressure in said chamber ranges from about 20 to about 200 milliTorr.

Claim 29

Dependent Claim 40 words

The process of claim 23 wherein said anode and cathode electrodes have a ratio of anode to cathode area of from about 2:1 to about 20:1 and an anode to cathode spacing of from about 5 to about 30 cm.

Claim 30

Dependent Claim 176 words

A plasma-assisted high pressure process for etching a material selected from the group consisting of aluminum and polysilicon in the fabrication of integrated circuit devices on semiconductor wafers characterized by the generation, in a vacuum etching chamber, of a plasma using one or more power sources having a frequency range of from about 100 MHz up to about 200 MHz to provide a sheath voltage low enough to avoid risk of damage to devices on said wafer during said etching and maintained at a power density level ranging from about 20 to about 40 watts/inch 2 of wafer area, while flowing one or more chlorine-containing gases and one or more inert gases into said vacuum etching chamber containing an anode and a wafer mounted on a cathode psaced from said anode a distance ranging from about 0.2 to less than about 5 cm., said vacuum chamber maintained at a pressure within a range of over 500 milliTorr to about 50 Torr to provide an aluminum or polysilicon removal rate of about 0.2 to about 1 micron/minute.

Claim 31

Dependent Claim 176 words

A plasma-assisted high pressure process for etching a material selected from the group consisting of aluminum and polysilicon in the fabrication of integrated circuit devices on semiconductor wafers characterized by the generation, in a vacuum etching chamber, of a plasma using one or more power sources having a frequency range of from about 100 MHz up to about 200 MHz to provide a sheath voltage low enough to avoid risk of damage to devices on said wafer during said etching and maintained at a power density level ranging from about 20 to about 40 watts/inch 2 of wafer area, while flowing one or more chlorine-containing gases and one or more inert gases into said vacuum etching chamber containing an anode and a wafer mounted on a cathode psaced from said anode a distance ranging from about 0.2 to less than about 5 cm., said vacuum chamber maintained at a pressure within a range of over 500 milliTorr to about 50 Torr to provide an aluminum or polysilicon removal rate of about 0.2 to about 1 micron/minute.

Claim 32

Dependent Claim 27 words

The process of claim 25 wherein said high pressure plasma etching process is operated within a pressure range of from about 1 Torr to about 20 Torr.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1997-04-04	1997-10-04	1998-04-05	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2001-04-04	2001-10-04	2002-04-05	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2005-04-04	2005-10-04	2006-04-05	$7700.00	Window Closed / Lapsed

UHF/VHF plasma for use in forming integrated circuit structures on semiconductor wafers

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