High voltage thin film transistor having a linear doping profile and method for making

Claim 1

In a method of manufacturing high voltage thin film transistors the steps comprising (a) providing a thin layer of monocrystalline silicon over an oxide layer on a silicon substrate, (b) decreasing resistivity of said thin layer of silicon by uniformly introducing impurities into said thin layer of silicon, (c) forming a mask over said thin layer of silicon, said mask having a plurality of openings, each of said openings laterally increasing in dimension from that of a proceeding opening, (d) introducing impurities into said thin layer of silicon through said plurality of openings to form a plurality of doped regions of different width, (e) removing said mask, capping said thin layer of silicon with silicon nitride, and annealing to form a linear doping profile from said plurality of doped regions over a lateral distance of said thin layer of silicon, wherein said linear doping profile is formed with a minimum doping concentration at one end of said lateral distance and a maximum doping concentration at a second opposite end of said lateral distance, (f) removing said silicon nitride at regions beyond edges of said lateral distance, thermally oxidizing exposed areas of said thin layer of silicon, and thereafter removing remaining portions of said silicon nitride, and (g) forming a structure with said thin layer of silicon having said linear doping profile.