Direct write EC single metal layer

Claim 2

An engineering change network for a multi-chip, multi-layer module, comprising in combination: a top surface metal layer including plurality of C4 pads for connecting a chip to said multi-chip module and a satellite pad located adjacent each of said plurality of C4 pads and connected to a C4 pad by a short deleteable line segment; said top surface metal layer including a plurality of interrupted line segments arranged in rows and columns so that at least one of said interrupted line segments passes in close proximity to each C4 pad of said plurality of C4 pads, said row and columns of said interrupted line segments extending beyond a chip boundary and terminating within a chip pitch boundary; a global engineering change wiring pattern comprised of parallel X directed interrupted segments on a buried layer in said multi-layer module connected to top surface metal X direction global segments that connect said interrupted segments, said top surface metal X direction global segments disposed between said chip boundary and said chip pitch boundary; and a global engineering change wiring pattern comprised of parallel Y directed interrupted segments on a buried layer in said multi-layer module connected to top surface metal Y direction global segments that connect said interrupted segments, said top surface metal Y direction global segments disposed between said chip boundary and said chip pitch boundary.

Claim 3

An engineering change network for a multi-chip, multi-layer module, comprising in combination: a top surface metal layer including plurality of C4 pads for connecting a chip to said multi-chip module and a satellite pad located adjacent each of said plurality of C4 pads and connected to a C4 pad by a short deleteable line segment; said top surface metal layer including a plurality of interrupted line segments arranged in rows and columns so that at least one of said interrupted line segments passes in close proximity to each C4 pad of said plurality of C4 pads, said row and columns of said interrupted line segments extending beyond a chip boundary and terminating within a chip pitch boundary; a first global engineering change wiring pattern comprised of parallel X directed interrupted segments on a first buried layer in said multi-layer module connected to top surface metal X direction global segments that connect said interrupted segments, said top surface metal X direction global segments disposed between said chip boundary and said chip pitch boundary; a second global engineering change wiring pattern comprised of parallel Y directed interrupted segments on a second buried layer in said multi-layer module connected to top surface metal Y direction global segments that connect said interrupted segments, said top surface metal Y direction global segments disposed between said chip boundary and said chip pitch boundary; a third global engineering change wiring pattern comprised of parallel X directed interrupted segments on a third buried layer in said multi-layer module connected to top surface metal X direction global segments that connect said interrupted segments, said top surface metal X direction global segments disposed between said chip boundary and said chip pitch boundary; and a fourth global engineering change wiring pattern comprised of parallel Y directed interrupted segments on a fourth buried layer in said multi-layer module connected to top surface metal Y direction global segments that connect said interrupted segments, said top surface metal Y direction global segments disposed between said chip boundary and said chip pitch boundary.

Claim 4

An engineering change network for a multi-chip, multi-layer module, comprising in combination: a top surface metal layer including plurality of C4 pads for connecting a chip to said multi-chip module and a satellite pad located adjacent each of said plurality of C4 pads and connected to a C4 pad by a short deleteable line segment; said top surface metal layer including a plurality of interrupted line segments arranged in rows and columns so that at least one of said interrupted line segments passes in close proximity to each C4 pad of said plurality of C4 pads, said row and columns of said interrupted line segments extending beyond a chip boundary and terminating within a chip pitch boundary; a first global engineering change wiring pattern comprised of parallel X directed interrupted segments on a first buried layer in said multi-layer module connected to top surface metal X direction global segments that connect said interrupted segments, said top surface metal X direction global segments disposed between said chip boundary and said chip pitch boundary; a second global engineering change wiring pattern comprised of parallel Y directed interrupted segments on a second buried layer in said multi-layer module connected to top surface metal Y direction global segments that connect said interrupted segments, said top surface metal Y direction global segments disposed between said chip boundary and said chip pitch boundary; a third global engineering change wiring pattern comprised of parallel X directed interrupted segments on a third buried layer in said multi-layer module connected to top surface metal X direction global segments that connect said interrupted segments, said top surface metal X direction global segments disposed between said chip boundary and said chip pitch boundary; and a fourth global engineering change wiring pattern comprised of parallel Y directed interrupted segments on a fourth buried layer in said multi-layer module connected to top surface metal Y direction global segments that connect said interrupted segments, said top surface metal Y direction global segments disposed between said chip boundary and said chip pitch boundary.

Claim 5

An engineering change network for a multi-chip, multi-layer module as in claim 2, wherein said first and second buried layers are thin-film layers and said third and fourth layers are MLC layers.

Claim 6

An engineering change network for a multi-chip, multi-layer module as in claim 1, wherein said top surface metal layer further includes a pair of direction changing lines that surround said plurality of C4 pads, said direction changing lines located outside said chip boundary and inside said chip pitch boundary.

Claim 7

An engineering change network for a multi-chip, multi-layer module as in claim 2, wherein said top surface metal layer further includes a pair of direction changing lines that surround said plurality of C4 pads, said direction changing lines located outside said chip boundary and inside said chip pitch boundary.