Semiconductor integrated circuit containing redundant memory element

Claim 2

A semiconductor integrated circuit comprising: a plurality of programmable circuits each including a plurality of fuses and a first transistor which has a gate subjected to an address decoded signal, a drain connected to first ends of the fuses, and a source connected to a common precharge node, wherein the address decoded signal results from decoding a first portion of an address signal for access to memory cells, and wherein the sources of the first transistors in the respective programmable circuits are connected to the common precharge node; a plurality of second transistors having gates subjected to a second portion of the address signal, sources connected to a first power supply line, and drains coupled to second ends of the fuses in each of the programmable circuits respectively, wherein the second portion of the address signal differs from the first portion of the address signal; and a third transistor having a gate subjected to a precharge control signal, a source connected to a second power supply line, and a drain connected to the common precharge node.

Claim 3

The semiconductor integrated circuit of claim 1, wherein each of the programmable circuits further includes a fourth transistor having a gate subjected to an inversion of the precharge control signal, a source connected to the second power supply line, and a drain connected to the first ends of the fuses, and a plurality of fifth transistors having gates subjected to the address decoded signal, sources connected to the drains of the second transistors respectively, and drains connected to the second ends of the fuses respectively.

Claim 4

A semiconductor integrated circuit comprising: first means for storing a state of a first bit of an address of a first defective memory cell; second means for storing a state of a first bit of an address of a second defective memory cell; third means for selecting one of the first means and the second means in response to a state of a second bit of an input address signal; fourth means for detecting whether or not a state of a first bit of the input address signal is equal to the state stored by the first means, and for detecting whether or not the state of the first bit of the input address signal is equal to the state stored by the second means; a common node; fifth means for outputting a spare memory cell selecting signal to the common node when the first means is selected by the third means and the fourth means detects that the state of the first bit of the input address signal is equal to the state stored by the first means, and for outputting the spare memory cell selecting signal when the second means is selected by the third means and the fourth means detects that the state of the first bit of the input address signal is equal to the state stored by the second means.

Claim 5

A semiconductor integrated circuit comprising: first means for storing a state of a first bit of an address of a first defective memory cell; second means for storing a state of a first bit of an address of a second defective memory cell; third means for selecting one of the first means and the second means in response to a state of a second bit of an input address signal; fourth means for detecting whether or not a state of a first bit of the input address signal is equal to the state stored by the first means, and for detecting whether or not the state of the first bit of the input address signal is equal to the state stored by the second means; a common node; fifth means for outputting a spare memory cell selecting signal to the common node when the first means is selected by the third means and the fourth means detects that the state of the first bit of the input address signal is equal to the state stored by the first means, and for outputting the spare memory cell selecting signal when the second means is selected by the third means and the fourth means detects that the state of the first bit of the input address signal is equal to the state stored by the second means.

Claim 6

A semiconductor integrated circuit comprising: a common precharge node; first means for precharging the common precharge node to a charged state; second means for storing a state of a first bit of an address of a first defective memory cell; third means for storing a state of a first bit of an address of a second defective memory cell; fourth means for selecting one of the second means and the third means in response to a state of a second bit of an input address signal; fifth means for detecting whether or not a state of a first bit of the input address signal is equal to the state stored by the second means, and for detecting whether or not the state of the first bit of the input address signal is equal to the state stored by the third means; sixth means for holding common precharge node in the charged state when the second means is selected by the fourth means and the fifth means detects that the state of the first bit of the input address signal is equal to the state stored by the second means, and for holding the common precharge node in the charged state when the third means is selected by the fourth means and the fifth means detects that the state of the first bit of the input address signal is equal to the state stored by the third means; and seventh means for discharging the common precharge node from the charged state when the fifth means detects that the state of the first bit of the input address signal is not equal to any of the states stored by the second and third means.

Claim 7

A semiconductor integrated circuit comprising: a common precharge node; first means for precharging the common precharge node to a charged state; second means for storing a state of a first bit of an address of a first defective memory cell; third means for storing a state of a first bit of an address of a second defective memory cell; fourth means for selecting one of the second means and the third means in response to a state of a second bit of an input address signal; fifth means for detecting whether or not a state of a first bit of the input address signal is equal to the state stored by the second means, and for detecting whether or not the state of the first bit of the input address signal is equal to the state stored by the third means; sixth means for holding common precharge node in the charged state when the second means is selected by the fourth means and the fifth means detects that the state of the first bit of the input address signal is equal to the state stored by the second means, and for holding the common precharge node in the charged state when the third means is selected by the fourth means and the fifth means detects that the state of the first bit of the input address signal is equal to the state stored by the third means; and seventh means for discharging the common precharge node from the charged state when the fifth means detects that the state of the first bit of the input address signal is not equal to any of the states stored by the second and third means.