Abstract An integrated circuit having a memory, and a method of operating the same, which provides for improved test efficiency. The memory includes static random access memory cells which power up in a preferred state; the preferred state draws less standby power, and is less susceptible to noise and other undesired effects which could cause upset of the stored data state. The method of testing the memory includes writing the memory cells with the complement of the preferred data state, so that all memory cells contain the higher current state; measurement of the standby current after the writing of the complement of the preferred data state will thus measure the worst case standby current. The method of testing may also include a disturb test, where the cell under test, or a neighboring cell in an adjacent row, is repeatedly accessed; such disturbing thus performs the worst case test, since the preferred state is more stable than its complement. Circuitry for performing the inverted write-back of the stored contents is also disclosed, so that such write-back may be performed without requiring read and write operations from the external terminals of the circuit.
A method of testing a read/write memory in an integrated circuit, said memory including a plurality of memory cells arranged in rows and columns, comprising: applying a bias voltage to said memory, said plurality of memory cells each storing a preferred data state responsive to said applying; sensing the state of a first one of said plurality of memory cells; and rewriting the logical complement of the sensed state into said memory cell; wherein said read/write memory has a data output terminal; and wherein the state of said first one of said plurality of memory cells is not presented at said data output terminal as a result of said sensing step.
Claim 2
Independent Claim
111 words
A method of testing a read/write memory in an integrated circuit, said memory including a plurality of memory cells arranged in rows and columns, comprising: applying a bias voltage to said memory, said plurality of memory cells each storing a preferred data state responsive to said applying; sensing the state of a first one of said plurality of memory cells; and rewriting the logical complement of the sensed state into said memory cell; wherein said read/write memory has a data output terminal; and wherein the state of said first one of said plurality of memory cells is not presented at said data output terminal as a result of said sensing step.
Claim 3
Dependent Claim
49 words
The method of claim 1, wherein each of said plurality of memory cells draws less current when storing the preferred data state than when storing the complement of said preferred data state; and further comprising: after said rewriting step, measuring the current drawn by said plurality of memory cells.
Claim 4
Dependent Claim
47 words
The method of claim 1, further comprising: after said rewriting step, accessing said first one of said plurality of memory cells a plurality of times; and after said accessing step, comparing the contents of said first memory cell to the data state written in said rewriting step.
Claim 5
Dependent Claim
57 words
The method of claim 1, further comprising: after said rewriting step, accessing, a plurality of times, a memory cell in a row adjacent to that of said first one of said plurality of memory cells; and after said accessing step, comparing the contents of said first memory cell to the data state written in said rewriting step.