Extremely low current load device for integrated circuit

Claim 2

In an integrated circuit memory having a drain supply node and a source supply node, a binary memory cell comprising: first and second complementary data input-output nodes, each of the nodes providing one d.c. current impedance path and one higher d.c. current impedance path corresponding to each binary logic state, respectively; first and second insulated gate field effect transistors the channels of which electrically connect the first and second data nodes, respectively, to the source supply node, the gate of the first transistor being electrically coupled to the second data node, and the gate of the second transistor being electrically coupled to the first data node; and, first and second impedance means electrically connecting the drain supply node to the first and second data nodes, respectively, each impedance means including a body of substantially intrinsic semiconductor material defining a conductive path and a doping of extrinsic conductivity impurities disposed within at least one defined region of the intrinsic body, at least one intrinsic-extrinsic junction being defined by the interface of the doped extrinsic region within the intrinsic body, and forming a series electrical path from the drain supply node to the corresponding data node.

Claim 3

The combination as claimed in claim 1 wherein the drain supply node, when charged, is characterized by a positive electrical potential with respect to the potential of the source supply node, the doping of extrinsic impurities being of the N-conductivity type and the intrinsic semiconductor material being of the P-conductivity type.

Claim 4

The combination as defined in claim 2 including a doping of P-conductivity impurities disposed throughout the intrinsic body, the magnitude of the P-conductivity impurity concentration being small as compared with the magnitude of the N-conductivity impurity concentration.

Claim 5

The combination as defined in claim 1 wherein the drain supply node, when charged, is characterized by a negative electrical potential with respect to the potential of the source supply node, the doping of the extrinsic impurities being of the P-conductivity type and the intrinsic semiconductor material being of the N-conductivity type.

Claim 6

The combination as defined in claim 4 including a doping of N-conductivity impurities disposed throughout the intrinsic body, the magnitude of the N-conductivity impurity concentration being small as compared with the magnitude of the P-conductivity impurity concentration.

Claim 7

In an integrated circuit memory having a drain supply node and a source supply node, a binary memory cell comprising: first and second complementary data input-output nodes, each of the nodes providing one d.c. current impedance path and one higher d.c. current impedance path corresponding to each binary logic state, respectively; first and second insulated gate field effect transistors the channels of which electrically connect the first and second data nodes, respectively, to the source supply node, the gate of the first transistor being electrically coupled to the second data node, and the gate of the second transistor being electrically coupled to the first data node; and first and second impedance means electrically connecting the drain supply node to the first and second data nodes, respectively, each impedance means including a body of substantially intrinsic semiconductor material defining a conductive path and having extrinsic impurities disposed within two separately defined regions of the intrinsic body, the two extrinsic regions being of the same conductivity type, intrinsic-extrinsic junctions being defined by the interface of the extrinsic regions with the remaining intrinsic body, and defining a series path for the flow of current from the drain supply node to the corresponding data node.

Claim 8

In an integrated circuit memory having a drain supply node and a source supply node, a binary memory cell comprising: first and second complementary data input-output nodes, each of the nodes providing one d.c. current impedance path and one higher d.c. current impedance path corresponding to each binary logic state, respectively; first and second insulated gate field effect transistors the channels of which electrically connect the first and second data nodes, respectively, to the source supply node, the gate of the first transistor being electrically coupled to the second data node, and the gate of the second transistor being electrically coupled to the first data node; and first and second impedance means electrically connecting the drain supply node to the first and second data nodes, respectively, each impedance means including a body of substantially intrinsic semiconductor material defining a conductive path and having extrinsic impurities disposed within two separately defined regions of the intrinsic body, the two extrinsic regions being of the same conductivity type, intrinsic-extrinsic junctions being defined by the interface of the extrinsic regions with the remaining intrinsic body, and defining a series path for the flow of current from the drain supply node to the corresponding data node.

Claim 9

The combination as defined in claim 6 wherein the drain supply node, when charged, is characterized by a positive electrical potential with respect to the potential of the source supply node, the doping of extrinsic impurities being of the N-conductivity type and the intrinsic semiconductor material being of the P-conductivity type.

Claim 10

The combination as defined in claim 7 including a diffusion of P-conductivity impurities disposed throughout the intrinsic body, the magnitude of the concentration of P-conductivity impurities being small as compared with the magnitude of the concentrations of N-conductivity impurities.

Claim 11

The combination as defined in claim 6 wherein the drain supply node, when charged, is characterized by a negative electrical potential with respect to the potential of the source supply node, the doping of extrinsic impurities being of the P-conductivity type and the intrinsic semiconductor material being of the P-conductivity type.

Claim 12

The combination as defined in claim 9 including a diffusion of N-conductivity impurities disposed throughout the intrinsic body, the magnitude of the concentration of N-conductivity impurities being small as compared with the magnitude of the concentration of P-conductivity impurities.

Claim 13

In combination with an integrated circuit of the type including a substrate of an extrinsic semiconductor material of a first conductivity type and an insulated gate field effect transistor disposed on the substrate, the transistor including source and drain elongated regions of extrinsic semiconductor material of the second conductivity type disposed within the substrate extending substantially parallel to each other and defining a channel region in the substrate therebetween, and an insulated gate disposed over the channel region, an impedance device connected to conduct current from a power supply node through the channel defined by the source and drain regions in response to an electrical potential applied to the insulated gate, the impedance device comprising at least one intrinsic-extrinsic junction of a substantially pure, intrinsic semiconductor material and a doping of extrinsic conductivity impurities disposed within a region of the intrinsic semiconductor material, the impurities being a selected conductivity type, the magnitude of the conductivity of the intrinsic semiconductor material being substantially less than the conductivity of the extrinsic semiconductor material, the conductivity of the extrinsic semiconductor material being either N-type or P-type.

Claim 14

In combination with an integrated circuit of the type including a substrate of an extrinsic semiconductor material of a first conductivity type and an insulated gate field effect transistor disposed on the substrate, the transistor including source and drain elongated regions of extrinsic semiconductor material of the second conductivity type disposed within the substrate extending substantially parallel to each other and defining a channel region in the substrate therebetween, and an insulated gate disposed over the channel region, an impedance device connected to conduct current from a power supply node through the channel defined by the source and drain regions in response to an electrical potential applied to the insulated gate, the impedance device comprising at least one intrinsic-extrinsic junction of a substantially pure, intrinsic semiconductor material and a doping of extrinsic conductivity impurities disposed within a region of the intrinsic semiconductor material, the impurities being a selected conductivity type, the magnitude of the conductivity of the intrinsic semiconductor material being substantially less than the conductivity of the extrinsic semiconductor material, the conductivity of the extrinsic semiconductor material being either N-type or P-type.

Claim 15

The impedance device defined in claim 11 wherein the power supply node, when energized, has a positive polarity providing a positive potential difference for the drain potential with respect to the source potential in response to the flow of current from the power supply node through the channel, the conductivity of the extrinsic semiconductor material comprising the source and drain regions and comprising the extrinsic region of the junction being N-type.

Claim 16

The impedance device defined in claim 11 wherein the power supply node, when energized, has a negative polarity providing a negative potential difference for the drain potential with respect to the source potential in response to the flow of current from the power supply node through the channel, the conductivity of the extrinsic semiconductor material comprising the source and drain regions being P-type.

Claim 17

The impedance device defined in claim 11 wherein the elemental semiconductor material comprising the substrate and the intrinsic material of the junction is polycrystalline silicon.

Claim 18

In an integrated circuit memory having a drain supply node and a source supply node disposed on a semiconductor substrate, a binary memory cell comprising: first and second insulated gate field effect transistors disposed on the substrate, each transistor having portions defining a source, a drain and a gate, the sources and drains of each transistor being formed by elongated diffused regions within the substrate, the source and drain elongated diffused regions of each transistor extending substantially parallel to each other and defining a continuous channel region in the substrate therebetween; a layer of insulating material disposed over the channel region of each transistor; the gate of each transistor being formed by a continuous semiconductor gate strip having a gate defining portion over-lying the insulating material over the associated channel region and a gate interconnect portion; the source diffusion of each transistor being electrically connected to the source supply node; the drain diffusion of the first transistor being connected to the gate portion of the second transistor thereby defining a first data node; the drain diffusion of the second transistor being connected to the gate portion of the first transistor thereby defining a second data node; and, the gate interconnect portions including the first and second impedance means electrically connecting the drain supply node to the corresponding data nodes, each impedance means including a body of substantially intrinsic semiconductor material and a doping of extrinsic conductivity impurities disposed within at least one defined region of the intrinsic body, at least one intrinsic-extrinsic junction being defined by the interface of doped extrinsic region within the intrinsic body, and forming a series electrical path from the drain supply node to the corresponding data node.

Claim 19

In an integrated circuit memory having a drain supply node and a source supply node disposed on a semiconductor substrate, a binary memory cell comprising: first and second insulated gate field effect transistors disposed on the substrate, each transistor having portions defining a source, a drain and a gate, the sources and drains of each transistor being formed by elongated diffused regions within the substrate, the source and drain elongated diffused regions of each transistor extending substantially parallel to each other and defining a continuous channel region in the substrate therebetween; a layer of insulating material disposed over the channel region of each transistor; the gate of each transistor being formed by a continuous semiconductor gate strip having a gate defining portion over-lying the insulating material over the associated channel region and a gate interconnect portion; the source diffusion of each transistor being electrically connected to the source supply node; the drain diffusion of the first transistor being connected to the gate portion of the second transistor thereby defining a first data node; the drain diffusion of the second transistor being connected to the gate portion of the first transistor thereby defining a second data node; and, the gate interconnect portions including the first and second impedance means electrically connecting the drain supply node to the corresponding data nodes, each impedance means including a body of substantially intrinsic semiconductor material and a doping of extrinsic conductivity impurities disposed within at least one defined region of the intrinsic body, at least one intrinsic-extrinsic junction being defined by the interface of doped extrinsic region within the intrinsic body, and forming a series electrical path from the drain supply node to the corresponding data node.

Claim 20

The integrated circuit memory as defined in claim 15 wherein the semiconductor substrate and the semiconductor gate strip each comprise polycrystalline silicon.

Claim 21

In an integrated circuit memory having a drain supply node and a source supply node disposed on a semiconductor substrate, a binary memory cell comprising: first and second insulated gate field effect transistors disposed on the substrate, each transistor having portions defining a source, a drain and a gate, the sources and drains of each transistor being formed by elongated diffused regions within the substrate, the source and drain elongated diffused regions of each transistor extending substantially parallel to each other and defining a continuous channel region in the substrate therebetween; a layer of insulating material disposed over the channel region of each transistor; the gate of each transistor being formed by a continuous semiconductor gate strip having a gate defining portion over-lying the insulating material over the associated channel region and a gate interconnect portion; the source diffusion of each transistor being electrically connected to the source supply node; the drain diffusion of the first transistor being connected to the gate portion of the second transistor thereby defining a first data node; the drain diffusion of the second transistor being connected to the gate portion of the first transistor thereby defining a second data node; and, the gate interconnect portions including the first and second impedance means electrically connecting the drain supply node to the corresponding data nodes, each impedance means including a body of substantially intrinsic semiconductor material having two terminal regions doped with extrinsic impurities of an opposite conductivity to the intrinsic body of series of p-n junctions for the flow of current from the drain supply node to the corresponding data node.

Claim 22

In an integrated circuit memory having a drain supply node and a source supply node disposed on a semiconductor substrate, a binary memory cell comprising: first and second insulated gate field effect transistors disposed on the substrate, each transistor having portions defining a source, a drain and a gate, the sources and drains of each transistor being formed by elongated diffused regions within the substrate, the source and drain elongated diffused regions of each transistor extending substantially parallel to each other and defining a continuous channel region in the substrate therebetween; a layer of insulating material disposed over the channel region of each transistor; the gate of each transistor being formed by a continuous semiconductor gate strip having a gate defining portion over-lying the insulating material over the associated channel region and a gate interconnect portion; the source diffusion of each transistor being electrically connected to the source supply node; the drain diffusion of the first transistor being connected to the gate portion of the second transistor thereby defining a first data node; the drain diffusion of the second transistor being connected to the gate portion of the first transistor thereby defining a second data node; and, the gate interconnect portions including the first and second impedance means electrically connecting the drain supply node to the corresponding data nodes, each impedance means including a body of substantially intrinsic semiconductor material having two terminal regions doped with extrinsic impurities of an opposite conductivity to the intrinsic body of series of p-n junctions for the flow of current from the drain supply node to the corresponding data node.