Receiver circuit with smart squelch

Claim 1

A receiver for filtering an incoming data signal that includes first and second differential inputs, the receiver circuit comprising; (a) a comparator that responds to the differential inputs by generating a positive output pulse when the difference in signal level between the differential inputs exceeds a preselected positive threshold level and by generating a negative output pulse when the difference in signal level is less than a preselected negative threshold level; (b) a first pulse width timer connected to receive positive output pulses from the comparator and that generates an active positive pulse output signal when a positive output pulse has a pulse width greater than a selected minimum pulse width; (c) a second pulse width timer connected to receive negative output pulses from the comparator and that generates an active negative pulse output signal when a negative pulse has a pulse width greater than the selected minimum pulse width; (d) first maximum pulse width timer means connected to the first and second pulse width timers for generating a first active long pulse output signal if a first received pulse, which may be either an active positive pulse output signal or active negative pulse output signal, has a pulse width less than a preselected maximum pulse width; (e) second maximum pulse width timer means connected to the first and second pulse width timers for generating a second active long pulse output signal if a second received pulse, received subsequent to and of opposite polarity with respect to the first received pulse, has a pulse width less than the preselected maximum pulse width; and (f) receive data trigger means responsive the first received pulse and to a third received pulse of the same polarity as the first received pulse for generating a receive data output signal.